公开(公告)号：US20140047269A1

公开(公告)日：2014-02-13

申请号：US13960826

申请日：2013-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： BOGEUN KIM

IPC: G06F11/14

CPC classification number: G06F11/1402 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the NVRAM.

Abstract translation: 包括非易失性随机存取存储器（NVRAM）和NAND闪速存储器的存储器系统的操作方法包括： 响应于读取请求执行指向目标存储器单元的正常读取操作，确定作为正常读取操作的结果已经发生读取失败，然后根据对应于存储器单元的反复执行针对目标存储器单元的重试操作 第一次读取重试方案，直到通过读取重试迭代成功读取目标存储器单元，并且将通过读取重试迭代关联的通过信息存储在NVRAM中。

公开(公告)号：US20150348633A1

公开(公告)日：2015-12-03

申请号：US14747786

申请日：2015-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON ,  MOOSUNG KIM ,  HYUNJUN YOON

IPC: G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。

公开(公告)号：US20140376312A1

公开(公告)日：2014-12-25

申请号：US14316023

申请日：2014-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。