公开(公告)号：US20130128671A1

公开(公告)日：2013-05-23

申请号：US13625114

申请日：2012-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG-HWAN SHIN ,  KITAE PARK ,  HYUN-WOOK PARK ,  JUN-HEE LEE

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/06

Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.

Abstract translation: 公开了一种闪速存储器件和编程方法，包括： 接收缓冲器数据，并在缓冲器数据的高速模式和可靠性模式之间确定，并且在确定将缓冲器数据存储在第一缓冲区域中的可靠性模式时，并且在确定将第二缓冲器数据存储在第二缓冲器数据中的高速模式 缓冲区。 闪速存储器的存储单元阵列包括分为第一缓冲区域和第二缓冲区域的主区域和单独指定的缓冲区域。

公开(公告)号：US20150348633A1

公开(公告)日：2015-12-03

申请号：US14747786

申请日：2015-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON ,  MOOSUNG KIM ,  HYUNJUN YOON

IPC: G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。

公开(公告)号：US20140376312A1

公开(公告)日：2014-12-25

申请号：US14316023

申请日：2014-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。