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    SEMICONDUCTOR MEMORY DEVICE
    12.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320076A1

    公开(公告)日：2023-10-05

    申请号：US17983489

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., LTD.

    Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10814 ,  G11C5/063

    Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210125989A1

    公开(公告)日：2021-04-29

    申请号：US16986367

    申请日：2020-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    SEMICONDUCTOR DEVICE
    15.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210036020A1

    公开(公告)日：2021-02-04

    申请号：US16942093

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Han PARK ,  Yong Seok KIM ,  Hui-Jung KIM ,  Satoru YAMADA ,  Kyung Hwan LEE ,  Jae Ho HONG ,  Yoo Sang HWANG

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L29/78

    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    18.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240064968A1

    公开(公告)日：2024-02-22

    申请号：US18321511

    申请日：2023-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woo Young CHOI ,  Hui-Jung KIM ,  Ji Hoon SUNG ,  Ga Eun CHOI ,  Sang Kyu SUN

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

    Abstract: Provided is a semiconductor memory device comprising an active region extending in a cell isolation layer, wherein the active region includes a first region and a second region; a bit line intersects the active region; a bit line contact between a substrate and the bit line, wherein the bit line contact is electrically connected to the first region; a bit line spacer that is on side surfaces of the bit line and the bit line contact; a node pad on a lateral side of the bit line spacer, wherein the node pad is electrically connected to the second region; a storage contact that is on the node pad and on a side surface of the bit line spacer, wherein the storage contact includes a first part having a first width and a second part having a second width different from the first width.

    SEMICONDUCTOR MEMORY DEVICE
    19.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320080A1

    公开(公告)日：2023-10-05

    申请号：US18093561

    申请日：2023-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyeok AHN ,  Woojin JEONG ,  Hui-Jung KIM

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

    Abstract: A semiconductor memory device includes an active portion defined by a device isolation pattern, the active portion including a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion, a word line provided on the active portion and extending in a first direction, a bit line provided on the word line and extending in a second direction crossing the first direction, a bit line contact provided between the bit line and the first impurity region of the active portion, a storage node pad provided on the second impurity region of the active portion, and a storage node contact provided on the storage node pad and at a side of the bit line.

    SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230055499A1

    公开(公告)日：2023-02-23

    申请号：US17805706

    申请日：2022-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

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