公开(公告)号：US09780019B2

公开(公告)日：2017-10-03

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US20170025335A1

公开(公告)日：2017-01-26

申请号：US15202765

申请日：2016-07-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/45

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L33/62 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.

Abstract translation: 根据实施例，提供了半导体部件，其包括具有器件接收区域的引线框架，一个或多个引线框架引线以及结合到器件接收区域的第一部分的至少一个绝缘金属衬底。 第一半导体器件安装到第一绝缘金属衬底，第一半导体器件由III-N半导体材料构成。 第一电互连耦合在第一半导体器件的第一载流端子和管芯接收区域的第二部分之间。 根据另一实施例，方法包括提供包括III-N半导体衬底材料的第一半导体芯片和包括硅基半导体衬底的第二半导体芯片。 第一半导体芯片安装在第一基板上，第二半导体芯片安装在第二基板上。 第一半导体芯片电耦合到第二半导体芯片。

公开(公告)号：US20150084153A1

公开(公告)日：2015-03-26

申请号：US14160273

申请日：2014-01-21

Applicant: Semiconductor Components Industries, LLC

Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Mingjiao Liu ,  Michael Thomason

IPC: H01L29/36 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66143 ,  H01L29/8725

Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.

Abstract translation: 肖特基器件包括多个台面结构，其中一个或多个台面结构包括具有多浓度掺杂剂分布的掺杂区域。 根据实施例，肖特基器件由第一导电类型的半导体材料形成。 在半导体材料中形成具有人行道和地板的沟槽，以形成多个台面结构。 在至少一个沟槽中形成具有多浓度杂质分布的掺杂区域，其中具有多浓度杂质分布的掺杂区域的杂质材料是第二导电类型。 形成具有具有多浓度杂质分布的掺杂区域的台面结构中的至少一个的肖特基接触。

公开(公告)号：US10438932B2

公开(公告)日：2019-10-08

申请号：US15954326

申请日：2018-04-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang Zhou ,  Yusheng Lin ,  Mingjiao Liu

IPC: H01L25/07 ,  H01L29/739 ,  H01L25/00 ,  H01L23/538 ,  H01L25/11 ,  H01L25/065 ,  H01L41/083 ,  H01L23/00

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US09972607B2

公开(公告)日：2018-05-15

申请号：US15231277

申请日：2016-08-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang Zhou ,  Yusheng Lin ,  Mingjiao Liu

IPC: H01L25/07 ,  H01L29/739 ,  H01L25/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/11 ,  H01L25/065 ,  H01L41/083

CPC classification number: H01L25/071 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US09818677B2

公开(公告)日：2017-11-14

申请号：US15202765

申请日：2016-07-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L23/373 ,  H01L33/62 ,  H01L29/20

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L33/62 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.

公开(公告)号：US11670706B2

公开(公告)日：2023-06-06

申请号：US16947085

申请日：2020-07-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Meng-Chia Lee ,  Ralph N. Wall ,  Mingjiao Liu ,  Shamsul Arefin Khan ,  Gordon M. Grivna

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/401 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/42376 ,  H01L29/66348

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

公开(公告)号：US10930524B2

公开(公告)日：2021-02-23

申请号：US16406899

申请日：2019-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Mingjiao Liu

IPC: H01L21/48 ,  H01L29/20 ,  H01L23/00 ,  H01L21/52 ,  H01L23/492 ,  H01L23/498 ,  H01L25/065 ,  H01L23/495

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.

公开(公告)号：US10388539B2

公开(公告)日：2019-08-20

申请号：US15202917

申请日：2016-07-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Mingjiao Liu

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L29/20 ,  H01L23/492 ,  H01L23/495 ,  H01L23/498

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.

公开(公告)号：US20190058056A1

公开(公告)日：2019-02-21

申请号：US15884779

申请日：2018-01-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mingjiao Liu ,  Shamsul Arefin Khan ,  Gordon M. Grivna ,  Meng-Chia Lee ,  Ralph N. Wall

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.