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    METHOD OF FABRICATING GRAPHENE NANO-MESH
    12.
    发明申请
    METHOD OF FABRICATING GRAPHENE NANO-MESH 有权
    制作石墨纳米网的方法

    公开(公告)号：US20170069436A1

    公开(公告)日：2017-03-09

    申请号：US15066780

    申请日：2016-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooho LEE ,  Yongsung KIM ,  Changseung LEE

    IPC: H01G11/86 ,  C23C16/50 ,  C23C16/40 ,  C23C16/455 ,  H01G11/36 ,  C23C16/26

    CPC classification number: H01G11/86 ,  H01G11/26 ,  H01G11/36 ,  H01G11/46 ,  H01G11/70 ,  Y02E60/13

    Abstract: Example embodiments relate to a method of fabricating a graphene nano-mesh by selectively growing an oxide layer on a defect site of a graphene layer and etching the oxide layer to form the graphene nano-mesh. The method includes forming a graphene layer on a catalyst layer, forming an oxide layer on a defect site of the graphene layer, forming the graphene nano-mesh including a plurality of openings by etching the oxide layer, and transferring, after removing the catalyst layer, the graphene nano-mesh onto a substrate.

    Abstract translation: 示例性实施例涉及通过选择性地生长石墨烯层的缺陷部位上的氧化物层并蚀刻氧化物层以形成石墨烯纳米网来制造石墨烯纳米网的方法。 该方法包括在催化剂层上形成石墨烯层，在石墨烯层的缺陷部位形成氧化层，通过蚀刻氧化层形成包括多个开口的石墨烯纳米网，并且在除去催化剂层之后转移 ，石墨烯纳米网到基底上。

    MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE
    14.
    发明申请
    MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE 有权

    公开(公告)号：US20250089270A1

    公开(公告)日：2025-03-13

    申请号：US18540222

    申请日：2023-12-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiyeon YANG ,  Haeryong KIM ,  Hajun SUNG ,  Changseung LEE

    IPC: H10B63/00 ,  H10B63/10

    Abstract: Provided are a memory device, a manufacturing method thereof, and an electronic apparatus including the memory device. The memory device may include a plurality of first conductors arranged apart from each other and perpendicular to a substrate, a second conductor extending perpendicular to the substrate, a chalcogenide layer extending perpendicular to the substrate between the plurality of first conductors and the second conductor, and a plurality of first diffusion barrier layers selectively arranged only on the plurality of first conductors between the plurality of first conductors and the chalcogenide layer. The plurality of first diffusion barrier layers each may include a carbon-based material.

    MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND METHOD OF IMPLEMENTING MULTI-LEVEL MEMORY BY USING THE MEMORY DEVICE
    20.
    发明申请
    MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND METHOD OF IMPLEMENTING MULTI-LEVEL MEMORY BY USING THE MEMORY DEVICE 有权

    公开(公告)号：US20250149084A1

    公开(公告)日：2025-05-08

    申请号：US18785752

    申请日：2024-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changseung LEE ,  Minwoo CHOI ,  Bonwon KOO ,  Hajun SUNG ,  Kiyeon YANG

    IPC: G11C11/56 ,  H10B63/00 ,  H10B99/00

    Abstract: Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.

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