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    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20180068712A1

    公开(公告)日：2018-03-08

    申请号：US15799073

    申请日：2017-10-31

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

    IPC: G11C11/417 ,  H01L27/11 ,  H01L29/10 ,  H01L23/528

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20160092293A1

    公开(公告)日：2016-03-31

    申请号：US14868238

    申请日：2015-09-28

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    Abstract translation: 本发明提供一种可以通过具有低面积开销的简单方法执行地址解码器的故障检测的半导体存储器件。 半导体存储器件包括：具有以矩阵排列的多个第一存储单元的第一存储器阵列; 与每个存储单元行对应地提供的多个字线; 地址解码器，用于根据输入的地址信息从字线中选择字线; 在列方向上与第一存储器阵列相邻设置的第二存储器阵列，具有多个第二存储单元，能够读取在先前存储的字线的选择中使用的地址信息，根据扩展的字线的选择 到第二存储器阵列; 以及比较电路，用于将输入地址信息与从第二存储器阵列读取的地址信息进行比较。

    SEMICONDUCTOR DEVICE
    14.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190027212A1

    公开(公告)日：2019-01-24

    申请号：US16143940

    申请日：2018-09-27

    Applicant: Renesas Electronics Corporation

    Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

    IPC: G11C11/417 ,  G11C11/413 ,  G11C11/412 ,  G11C11/41 ,  G11C5/14

    CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.

    MULTI-PORT MEMORY AND SEMICONDUCTOR DEVICE
    15.
    发明申请
    MULTI-PORT MEMORY AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20180122458A1

    公开(公告)日：2018-05-03

    申请号：US15674659

    申请日：2017-08-11

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII

    IPC: G11C11/418 ,  G11C11/419

    CPC classification number: G11C11/418 ,  G11C7/1018 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419

    Abstract: In a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a first start signal to a first state in response to generation of the first pulse signal, and resets the first start signal to a second state in response to a first delayed signal obtained by delaying the first start signal by a delay circuit. A second pulse signal generator circuit generates a second pulse signal following input of the first delayed signal. A first latch circuit sets a second start signal to the first state and holds this state in response to generation of the second pulse signal, and resets the second start signal to the second state in response to a second delayed signal obtained by delaying the second start signal by the delay circuit. The memory operates based on start signals.

    SEMICONDUCTOR MEMORY DEVICE
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180018211A1

    公开(公告)日：2018-01-18

    申请号：US15710803

    申请日：2017-09-20

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    SEMICONDUCTOR DEVICE
    19.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170103803A1

    公开(公告)日：2017-04-13

    申请号：US15389192

    申请日：2016-12-22

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Kazumasa YANAGISAWA

    IPC: G11C11/417 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

    SEMICONDUCTOR STORAGE DEVICE
    20.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20160351251A1

    公开(公告)日：2016-12-01

    申请号：US15232216

    申请日：2016-08-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII

    IPC: G11C11/418 ,  G11C11/419

    CPC classification number: G11C11/418 ,  G11C5/147 ,  G11C7/20 ,  G11C11/412 ,  G11C11/419

    Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

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