公开(公告)号：US11302773B2

公开(公告)日：2022-04-12

申请号：US16155694

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Haitao Cheng ,  Chao Song

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/532

Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

公开(公告)号：US20200066829A1

公开(公告)日：2020-02-27

申请号：US16106160

申请日：2018-08-21

Applicant: Qualcomm Incorporated

Inventor： Haitao CHENG ,  Chao Song ,  Ye Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01L23/522 ,  H01L27/08

Abstract: Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

公开(公告)号：US20190326057A1

公开(公告)日：2019-10-24

申请号：US15961594

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Haitao Cheng ,  Chao Song

IPC: H01G4/10 ,  H01G4/01 ,  H01L23/522

Abstract: Methods, systems, and devices for a finger metal-on-metal (FMOM) capacitor including a negative capacitance material are described. In one examples, a FMOM capacitor may include a first electrode and a second electrode. The FMOM capacitor may include a dielectric layer coating a first sidewall of the first electrode and a second sidewall of a second electrode. A portion of the first sidewall may be substantially parallel to a portion of the second sidewall. The FMOM capacitor may also include a negative capacitance material disposed in a channel between the first sidewall of the first electrode and the second sidewall of the second electrode. The negative capacitance material may extend in a direction that is substantially parallel to the portion of the first sidewall and the portion of the second sidewall.

公开(公告)号：US10431540B1

公开(公告)日：2019-10-01

申请号：US16039213

申请日：2018-07-18

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Chao Song ,  Ye Lu

IPC: H01L21/02 ,  H01L23/522 ,  H03F3/195 ,  H01L49/02 ,  H01L23/66

Abstract: A semiconductor device reduces parasitic capacitance between a metal-oxide-metal (MOM)/metal-insulator-metal (MIM) capacitors and a semiconductor substrate. The semiconductor device includes the semiconductor substrate (e.g., a silicon substrate, a III-V compound semiconductor substrate, or a silicon on insulator (SOI) substrate), a magnetic material layer, and a capacitor. The magnetic material layer is between the semiconductor substrate and the capacitor.

公开(公告)号：US10312891B1

公开(公告)日：2019-06-04

申请号：US16142476

申请日：2018-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chao Song ,  Zhengzheng Wu ,  Haitao Cheng ,  Ye Lu

IPC: H03K5/00 ,  H01L49/02 ,  H01L27/06 ,  H03K19/20

Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.

公开(公告)号：US20170257065A1

公开(公告)日：2017-09-07

申请号：US15191350

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Kevin Wang ,  Chao Song ,  Shyam Sivakumar

IPC: H03B5/24

CPC classification number: H03B5/24 ,  H03B5/26 ,  H03K3/03 ,  H03K3/0315 ,  H03K5/065 ,  H03K5/1252 ,  H03L7/099

Abstract: An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

公开(公告)号：US11533058B2

公开(公告)日：2022-12-20

申请号：US17125595

申请日：2020-12-17

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng Wu ,  Chao Song ,  Karthik Nagarajan

IPC: H03L7/085 ,  H03L7/197 ,  H03L7/099 ,  H03K3/037 ,  H03K5/00 ,  H03K19/20 ,  H03L7/093 ,  H04M1/725

Abstract: A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.

公开(公告)号：US11004784B2

公开(公告)日：2021-05-11

申请号：US16158742

申请日：2018-10-12

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Ye Lu ,  Chao Song

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01G4/06 ,  H01L49/02

Abstract: Certain aspects of the present disclosure provide a metal-on-metal (MoM) capacitor with metal layers, each layer having two different electrical conductors with orthogonally-arranged conductive arteries and orthogonally-oriented conductive fingers. One exemplary MoM capacitor generally includes a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a first electrical conductor providing a first node of the MoM capacitor and a second electrical conductor providing a second node of the MoM capacitor. According to aspects, the first electrical conductor comprises a first plurality of conductive fingers and the second electrical conductor comprises a second plurality of conductive fingers. Further, conductive fingers of the first plurality of conductive fingers are interdigitated with conductive fingers of the second plurality of conductive fingers. Additionally, the first electrical conductor in the first metal layer is oriented orthogonal to the second electrical conductor in the first metal layer.

公开(公告)号：US10972068B2

公开(公告)日：2021-04-06

申请号：US16023186

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Chao Song ,  Haitao Cheng ,  Ye Lu ,  Dongjiang Qiao

IPC: H03H7/30 ,  H03H1/02 ,  H03H3/00 ,  H03H7/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

公开(公告)号：US10665370B2

公开(公告)日：2020-05-26

申请号：US16058928

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Chao Song ,  Ye Lu

IPC: H01C3/02 ,  H01L49/02 ,  H01L27/02 ,  H01C17/04 ,  H01C3/16 ,  G06F30/36 ,  G06F30/3312

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.