公开(公告)号：US20140098448A1

公开(公告)日：2014-04-10

申请号：US13646109

申请日：2012-10-05

Applicant: QUALCOMM INCORPORATED

Inventor： Brian M. Henderson ,  Chiew-Guan Tan ,  Gregory A. Uvieghara ,  Reza Jalilizeinali

IPC: H02H9/04 ,  H01L21/44

CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

公开(公告)号：US11575259B2

公开(公告)日：2023-02-07

申请号：US17370894

申请日：2021-07-08

Applicant: QUALCOMM Incorporated

Inventor： Wen-Yi Chen ,  Reza Jalilizeinali ,  Sreeker Dundigal ,  Krishna Chaitanya Chillara ,  Gregory Lynch

IPC: H02H9/04 ,  H01L27/02

Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

公开(公告)号：US09977078B2

公开(公告)日：2018-05-22

申请号：US14339224

申请日：2014-07-23

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  LuVerne Ray Peterson

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31716 ,  G01R31/318513

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

公开(公告)号：US09800230B1

公开(公告)日：2017-10-24

申请号：US15197589

申请日：2016-06-29

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/00 ,  H03K3/012 ,  H03K17/22 ,  H03K3/037 ,  H03K5/19

CPC classification number: H03K3/012 ,  G06F1/24 ,  H03K3/0375 ,  H03K5/19 ,  H03K17/223

Abstract: A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

公开(公告)号：US09484911B2

公开(公告)日：2016-11-01

申请号：US14631347

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/01 ,  H03K17/26 ,  H03K17/18

CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

公开(公告)号：US20160025807A1

公开(公告)日：2016-01-28

申请号：US14339224

申请日：2014-07-23

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  LuVerne Ray Peterson

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31716 ,  G01R31/318513

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract translation: 提供了用于环回测试的电路和方法。 一个管芯将每个发射器（TX）的接收器（RX）以及每个接收器的TX都包含在内。 该架构被应用于每个位，因此，例如，在操作期间发送或接收32个数据位的管芯将具有32个收发器（每个位一个）。 专注于收发器之一，环回架构包括TX数据路径和RX数据路径，其通过诸如收发器之间的通孔的外部接点相互耦合。 芯片还包括馈送TX数据路径的发射时钟树和馈送RX数据路径的接收时钟树。 传输时钟树通过露出在芯片表面上的导电时钟节点馈送接收时钟树。 一些系统还包括时钟路径中的可变延迟。

公开(公告)号：US09184735B1

公开(公告)日：2015-11-10

申请号：US14254706

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：US09083176B2

公开(公告)日：2015-07-14

申请号：US13740102

申请日：2013-01-11

Applicant: QUALCOMM Incorporated

Inventor： Eugene Robert Worley ,  Sreeker Dundigal ,  Evan Siansuri ,  Reza Jalilizeinali ,  Michael Brunolli

IPC: H02H9/00 ,  H02H9/04 ,  G06F1/30 ,  H01L23/62

CPC classification number: H02H9/046 ,  G06F1/305 ,  H01L23/62 ,  H01L2924/0002 ,  H02H9/043 ,  H01L2924/00

Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.

Abstract translation: 在特定实施例中，电路包括耦合到电源和接地的电源，接地和钳位晶体管电路。 电路还包括禁止钳位电路。 禁止钳位电路耦合到电源，并且响应于第二电源输入，以通过修改施加到钳位晶体管电路的电容器的充电电流来选择性地禁止钳位晶体管电路。 在特定实施例中，修改充电电流包括实现第二充电路径。 启用第二充电路径使得能够以比通过第一充电路径对电容器充电相关的充电速率更高的充电速率对电容器进行充电。

公开(公告)号：US20140198414A1

公开(公告)日：2014-07-17

申请号：US13740102

申请日：2013-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： Eugene Robert Worley ,  Sreeker Dundigal ,  Evan Siansuri ,  Reza Jalilizeinali ,  Michael Brunolli

IPC: H02H9/04

CPC classification number: H02H9/046 ,  G06F1/305 ,  H01L23/62 ,  H01L2924/0002 ,  H02H9/043 ,  H01L2924/00

Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.

Abstract translation: 在特定实施例中，电路包括耦合到电源和接地的电源，接地和钳位晶体管电路。 电路还包括禁止钳位电路。 禁止钳位电路耦合到电源，并且响应于第二电源输入，以通过修改施加到钳位晶体管电路的电容器的充电电流来选择性地禁止钳位晶体管电路。 在特定实施例中，修改充电电流包括实现第二充电路径。 启用第二充电路径使得能够以比通过第一充电路径对电容器充电相关的充电速率更高的充电速率对电容器进行充电。

公开(公告)号：US20140091860A1

公开(公告)日：2014-04-03

申请号：US13683053

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: G05F1/565

CPC classification number: G05F1/565

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract translation: 公开了一种输入/输出（I / O）驱动器，其采用补偿电路来限制驱动器的器件之间的电压超过限定的阈值，以允许较低电压的器件实现驱动器的操作。 特别地，驱动器采用包括耦合在第一电压轨和驱动器的输出之间的第一和第二开关器件的上拉电路。 驱动器采用包括耦合在输出端和第二电压轨道之间的第三和第四开关器件的下拉电路。 I / O驱动器采用补偿电路，其被配置为在适当的时间向第一和第二开关器件之间的节点和第三和第四开关器件之间的节点施加补偿电压，以保持跨越第二和第三开关器件的相应电压 在驾驶员的操作期间，切换设备处于或低于定义的阈值，例如可靠性限制。