Patent search ap:("QUALCOMM INCORPORATED") AND inv:"Brian M. Henderson" Page 1

1.

发明申请
SEMICONDUCTOR DEVICE HAVING STACKED MEMORY ELEMENTS AND METHOD OF STACKING MEMORY ELEMENTS ON A SEMICONDUCTOR DEVICE 有权
Title translation: 具有堆叠存储器元件的半导体器件和在半导体器件上堆叠存储器元件的方法

公开(公告)号：US20140225280A1

公开(公告)日：2014-08-14

申请号：US13766218

申请日：2013-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： Brian M. Henderson , Shiqun Gu

IPC: H01L23/498 , H01L21/50

CPC classification number: H01L21/50 , H01L23/481 , H01L23/49827 , H01L23/49833 , H01L23/525 , H01L24/17 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17181 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H01L2924/0002 , H01L2924/00 , H01L2224/13099

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

Abstract translation: 半导体器件包括耦合到衬底的管芯，耦合到与衬底相对的管芯的表面的第一存储器件和耦合在与衬底相对的管芯的表面之间的耦合器件和第二存储器件至少部分地与第一存储器件重叠。还公开了以至少部分重叠的方式将第一和第二存储器件安装在管芯上的方法。

2.

发明申请
THROUGH-SUBSTRATE VIA WITH A FUSE STRUCTURE 审中-公开
Title translation: 通过保险丝结构通过基板

公开(公告)号：US20140266286A1

公开(公告)日：2014-09-18

申请号：US13801009

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran , Shiqun Gu , Brian M. Henderson , Michael Scott DiBattista , Babak Motamedi , George F. Gaut

IPC: H01L23/522 , H01L23/525 , G01R31/26 , G06F17/50

CPC classification number: H01L23/5256 , G01R31/026 , G01R31/2884 , G06F17/5068 , H01L23/481 , H01L2924/0002 , H01L2924/00

Abstract: A device includes a conductive via to provide an electrical path through a substrate. The device further includes a conductive element. The device further includes a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element. The conductive path enables testing of continuity of at least a portion of the conductive via. The fuse is configured to be disabled after the testing of the continuity of the conductive via.

Abstract translation: 一种器件包括导电通孔以提供通过衬底的电路径。该装置还包括导电元件。该器件还包括耦合到导电通孔并且耦合到导电元件的熔丝，以在导电通孔和导电元件之间提供导电路径。导电路径使得能够测试导电通孔的至少一部分的连续性。保险丝被配置为在测试导电通孔的连续性后禁用。

3.

发明授权
Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device 有权
Title translation: 具有层叠存储元件的半导体器件和将存储元件堆叠在半导体器件上的方法

公开(公告)号：US09041220B2

公开(公告)日：2015-05-26

申请号：US13766218

申请日：2013-02-13

Applicant: Qualcomm Incorporated

Inventor： Brian M. Henderson , Shiqun Gu

IPC: H01L23/498 , H01L21/50 , H01L25/065 , H01L25/18 , H01L23/48 , H01L23/525

CPC classification number: H01L21/50 , H01L23/481 , H01L23/49827 , H01L23/49833 , H01L23/525 , H01L24/17 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17181 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H01L2924/0002 , H01L2924/00 , H01L2224/13099

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

Abstract translation: 半导体器件包括耦合到衬底的管芯，耦合到与衬底相对的管芯的表面的第一存储器件和耦合在与衬底相对的管芯的表面之间的耦合器件和第二存储器件至少部分地与第一存储器件重叠。还公开了以至少部分重叠的方式将第一和第二存储器件安装在管芯上的方法。

4.

发明申请
ELECTROSTATIC DISCHARGE DIODE 有权
Title translation: 静电放电二极管

公开(公告)号：US20140327105A1

公开(公告)日：2014-11-06

申请号：US13887723

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran , Brian M. Henderson , Shiqun Gu , Chiew-Guan Tan , Jung Pill Kim , Taehyun Kim

IPC: H01L29/66 , H01L23/498 , H01L29/861

CPC classification number: H01L29/66128 , H01L21/304 , H01L21/762 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/535 , H01L23/60 , H01L25/0657 , H01L27/0255 , H01L27/0296 , H01L27/0694 , H01L27/0814 , H01L29/0649 , H01L29/66143 , H01L29/8611 , H01L29/872 , H01L2224/02372 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12032 , H01L2224/81 , H01L2924/00 , H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。该方法还包括在衬底的背面形成第一二极管。第一二极管耦合到第一通孔。

5.

发明申请
POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT STACKED INTEGRATED CIRCUITS 审中-公开
Title translation: 直接堆叠集成电路的功率分配和热解决方案

公开(公告)号：US20140225248A1

公开(公告)日：2014-08-14

申请号：US13783124

申请日：2013-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Brian M. Henderson , Shiqun Gu

IPC: H01L23/34 , H01L21/50

CPC classification number: H01L23/5384 , H01L21/50 , H01L23/3128 , H01L23/34 , H01L23/36 , H01L23/481 , H01L23/49811 , H01L23/5286 , H01L23/5383 , H01L23/5389 , H01L24/19 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/73259 , H01L2224/92224 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06544 , H01L2225/06548 , H01L2225/06586 , H01L2225/06589 , H01L2924/15184 , H01L2924/15311

Abstract: Some implementations provide an apparatus that includes a package substrate, a first die coupled to the package substrate, and a second die coupled to the first die. The die package also includes a heat spreader coupled to the second die, the heat spreader configured to (i) dissipate heat from the second die, and (ii) provide an electrical path for a power signal to the second die. In some implementations, the die package also includes a molding surrounding the first die and the second die. The die package also includes several through mold vias (TMVs) coupled to the heat spreader. The TMVs are configured to provide an electrical path for the power signal to the second die through the heat spreader. In some implementations, the TMVs traverse the molding.

Abstract translation: 一些实施方案提供了一种装置，其包括封装衬底，耦合到封装衬底的第一裸片以及耦合到第一裸片的第二裸片。模具封装还包括耦合到第二管芯的散热器，散热器配置成（i）从第二管芯散热，以及（ii）为第二管芯提供用于功率信号的电路径。在一些实施方案中，模具包装还包括围绕第一模具和第二模具的模制件。模具封装还包括耦合到散热器的多个通孔（TMV）。 TMV被配置为通过散热器为第二管芯提供电力信号的电路。在一些实施方案中，TMV穿过模制件。

6.

发明申请
ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS 有权
Title translation: 用于堆叠多芯片集成电路的静电保护

公开(公告)号：US20140098448A1

公开(公告)日：2014-04-10

申请号：US13646109

申请日：2012-10-05

Applicant: QUALCOMM INCORPORATED

Inventor： Brian M. Henderson , Chiew-Guan Tan , Gregory A. Uvieghara , Reza Jalilizeinali

IPC: H02H9/04 , H01L21/44

CPC classification number: H01L23/5256 , H01L23/3128 , H01L23/481 , H01L23/60 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/48091 , H01L2224/73257 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014

Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。多芯片模块封装完成后，保险丝可能会断开。

7.

发明授权
Electrostatic protection for stacked multi-chip integrated circuits 有权
Title translation: 堆叠多芯片集成电路的静电保护

公开(公告)号：US09184130B2

公开(公告)日：2015-11-10

申请号：US13646109

申请日：2012-10-05

Applicant: QUALCOMM Incorporated

Inventor： Brian M. Henderson , Chiew-Guan Tan , Gregory A. Uvieghara , Reza Jalilizeinali

IPC: H02H9/00 , H01L23/525 , H01L23/60 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/48

CPC classification number: H01L23/5256 , H01L23/3128 , H01L23/481 , H01L23/60 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/48091 , H01L2224/73257 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014

Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。多芯片模块封装完成后，保险丝可能会断开。