公开(公告)号：US11575259B2

公开(公告)日：2023-02-07

申请号：US17370894

申请日：2021-07-08

Applicant: QUALCOMM Incorporated

Inventor： Wen-Yi Chen ,  Reza Jalilizeinali ,  Sreeker Dundigal ,  Krishna Chaitanya Chillara ,  Gregory Lynch

IPC: H02H9/04 ,  H01L27/02

Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

公开(公告)号：US10911047B1

公开(公告)日：2021-02-02

申请号：US16743617

申请日：2020-01-15

Applicant: QUALCOMM Incorporated

Inventor： Rohit Shetty ,  Chiew-Guan Tan ,  Gregory Lynch

IPC: H03K19/003 ,  H03K19/00 ,  H03K3/356 ,  H03K3/012 ,  H03K19/0185

Abstract: Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.