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    Input/output (I/O) driver implementing dynamic gate biasing of buffer transistors
    2.
    发明授权
    Input/output (I/O) driver implementing dynamic gate biasing of buffer transistors 有权

    公开(公告)号：US09614529B1

    公开(公告)日：2017-04-04

    申请号：US15012696

    申请日：2016-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

    IPC: H03K3/00 ,  H03K19/0185

    CPC classification number: H03K19/018507 ,  H03K19/0016 ,  H03K19/018514

    Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

    Latch-based power-on checker
    3.
    发明授权
    Latch-based power-on checker 有权

    公开(公告)号：US09800230B1

    公开(公告)日：2017-10-24

    申请号：US15197589

    申请日：2016-06-29

    Applicant: QUALCOMM Incorporated

    Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

    IPC: H03K5/00 ,  H03K3/012 ,  H03K17/22 ,  H03K3/037 ,  H03K5/19

    CPC classification number: H03K3/012 ,  G06F1/24 ,  H03K3/0375 ,  H03K5/19 ,  H03K17/223

    Abstract: A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

    High voltage input receiver using low-voltage devices
    4.
    发明授权
    High voltage input receiver using low-voltage devices 有权

    公开(公告)号：US09735763B1

    公开(公告)日：2017-08-15

    申请号：US15083030

    申请日：2016-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Sumit Rao

    IPC: H03K5/08 ,  H03K19/003 ,  H03K5/24

    CPC classification number: H03K5/08 ,  G06F13/4072 ,  H03K5/24 ,  H03K19/00315 ,  H03K19/018514

    Abstract: An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

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