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    PACKAGE SUBSTRATES INCLUDING EMBEDDED CAPACITORS
    12.
    发明申请
    PACKAGE SUBSTRATES INCLUDING EMBEDDED CAPACITORS 审中-公开
    封装基板包括嵌入式电容器

    公开(公告)号：US20160055976A1

    公开(公告)日：2016-02-25

    申请号：US14468212

    申请日：2014-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

    IPC: H01G4/30 ,  H01L21/768 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L23/522 ,  H01G4/012

    CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L21/76802 ,  H01L21/7687 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated devices include a substrate, and a capacitor embedded within the substrate. The capacitor is configured to include a first electrode disposed on a first surface, a second electrode disposed on an opposing second surface, and a plurality of capacitor plates extending transverse between the first electrode and the second electrode. Each capacitor plate is electrically coupled to one of the first electrode or the second electrode. A plurality of vias are positioned to extend through the substrate to one of the first electrode or the second electrode. Other aspects, embodiments, and features are also included.

    Abstract translation: 集成器件包括衬底和嵌入衬底内的电容器。 电容器被配置为包括设置在第一表面上的第一电极，设置在相对的第二表面上的第二电极和在第一电极和第二电极之间横向延伸的多个电容器板。 每个电容器板电耦合到第一电极或第二电极之一。 定位多个通孔以将基板延伸到第一电极或第二电极之一。 还包括其他方面，实施例和特征。

    TOROID INDUCTOR IN AN INTEGRATED DEVICE
    13.
    发明申请
    TOROID INDUCTOR IN AN INTEGRATED DEVICE 有权
    集成器件中的电极电感器

    公开(公告)号：US20150115403A1

    公开(公告)日：2015-04-30

    申请号：US14063934

    申请日：2013-10-25

    Applicant: QUALCOMM Incorporated

    Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

    IPC: H01L49/02

    CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

    Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

    BANDPASS FILTER IMPLEMENTATION ON A SINGLE LAYER USING SPIRAL CAPACITORS
    14.
    发明申请
    BANDPASS FILTER IMPLEMENTATION ON A SINGLE LAYER USING SPIRAL CAPACITORS 有权
    使用螺旋电容器的单层滤波器实现

    公开(公告)号：US20140266508A1

    公开(公告)日：2014-09-18

    申请号：US13835211

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

    IPC: H03H7/01 ,  H03H3/00 ,  H01G4/40

    CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

    Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

    Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线。 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。

    Integrated device package comprising a tunable inductor
    15.
    发明授权
    Integrated device package comprising a tunable inductor 有权

    公开(公告)号：US10304623B2

    公开(公告)日：2019-05-28

    申请号：US15002174

    申请日：2016-01-20

    Applicant: QUALCOMM Incorporated

    Inventor： Young Kyu Song ,  John Jong Hoon Lee ,  Sangjo Choi

    IPC: G06F1/16 ,  H01F29/02 ,  G05B19/10 ,  H01F27/29 ,  H01F27/42 ,  H05K7/14 ,  H01L23/498 ,  H01L23/64 ,  H01L23/31

    Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

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