公开(公告)号：US09548446B2

公开(公告)日：2017-01-17

申请号：US15133018

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Matthias Georg Gottwald ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.

Abstract translation: 提供磁阻随机存取存储器（MRAM）中的磁隧道结（MTJ）器件及其制造方法，以实现高隧道磁阻（TMR），高垂直磁各向异性（PMA），良好的数据保留和 高水平的热稳定性。 MTJ装置包括第一自由铁磁层，合成反铁磁（SAF）耦合层和第二自由铁磁层，其中第一和第二自由铁磁层具有相反的磁矩。

公开(公告)号：US09524765B2

公开(公告)日：2016-12-20

申请号：US14460626

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22 ,  G11C7/24

CPC classification number: G11C11/1673 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C2213/78 ,  H01L27/228

Abstract: An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion.

Abstract translation: 一种装置包括差分MTJ对的第一磁隧道结（MTJ）装置。 该装置还包括差分MTJ对的第二MTJ装置。 第一MTJ装置包括具有高矫顽力部分的感测层。

公开(公告)号：US09508439B2

公开(公告)日：2016-11-29

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  G11C16/26 ,  H01L27/112

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US09502088B2

公开(公告)日：2016-11-22

申请号：US14499155

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Jisu Kim ,  Taehui Na ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract translation: 系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。 负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。 基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。 产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。 存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

公开(公告)号：US09373782B2

公开(公告)日：2016-06-21

申请号：US14518459

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Matthew Michael Nowak

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract translation: 存储器件可以包括磁性隧道结（MTJ）堆叠，底部电极（BE）层和接触层。 MTJ堆叠可以包括自由层，阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠，并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中，并且在BE层和MTJ堆叠之间形成界面。

公开(公告)号：US09343659B1

公开(公告)日：2016-05-17

申请号：US14625494

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).

Abstract translation: 磁阻随机存取存储器（MRAM）装置包括金属硬掩模上方的顶部电极或顶部触点，由于先进节点中的工艺限制，其具有有限的高度。 金属硬掩模设置在磁性隧道结（MTJ）上。 MTJ的顶部接触形成在介电层内，例如低介电常数（低k）或极低k层。 在顶部触点上方提供了另外的介电层，用于额外的连接，用于附加电路以形成三维集成电路（3D IC）。

公开(公告)号：US09324939B2

公开(公告)日：2016-04-26

申请号：US14321516

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Matthias Georg Gottwald ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.

Abstract translation: 提供磁阻随机存取存储器（MRAM）中的磁隧道结（MTJ）器件及其制造方法，以实现高隧道磁阻（TMR），高垂直磁各向异性（PMA），良好的数据保留和 高水平的热稳定性。 MTJ装置包括第一自由铁磁层，合成反铁磁（SAF）耦合层和第二自由铁磁层，其中第一和第二自由铁磁层具有相反的磁矩。

公开(公告)号：US20160012896A1

公开(公告)日：2016-01-14

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  G11C16/26 ,  H01L29/51

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US09224467B2

公开(公告)日：2015-12-29

申请号：US14147817

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

公开(公告)号：US09082962B2

公开(公告)日：2015-07-14

申请号：US14086054

申请日：2013-11-21

Applicant: QUALCOMM Incorporated

Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。