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公开(公告)号：US11107821B2
公开(公告)日：2021-08-31
申请号：US16412935
申请日：2019-05-15
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodoras E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L21/84 , H01L29/66 , H01L29/94 , H01L27/12 , G06F30/30 , G06F30/39 , G06F30/392 , G06F30/10 , H01L49/02 , H01L29/04 , H01L27/07 , H01L29/06 , H01L29/51 , H01L27/06
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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公开(公告)号：US10535662B2
公开(公告)日：2020-01-14
申请号：US14601288
申请日：2015-01-21
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L27/07 , H01L27/12 , H01L29/94 , H01L21/28 , H01L29/78 , H01L21/84 , G06F17/50 , H01L29/66 , H01L49/02 , H01L29/04 , H01L29/06 , H01L29/51 , H01L27/06
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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公开(公告)号：US20180294334A1
公开(公告)日：2018-10-11
申请号：US16005782
申请日：2018-06-12
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/34 , H01L21/38 , H01L21/311 , H01L21/321
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
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公开(公告)号：US10068967B2
公开(公告)日：2018-09-04
申请号：US15604719
申请日：2017-05-25
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/38 , H01L21/34 , H01L21/02 , H01L21/311 , H01L21/321
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
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公开(公告)号：US20180225405A1
公开(公告)日：2018-08-09
申请号：US15940009
申请日：2018-03-29
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： G06F17/50 , H01L29/94 , H01L29/04 , H01L49/02 , H01L27/12 , H01L27/108 , H01L27/07 , H01L29/66 , H01L21/84 , H01L27/06
CPC分类号： H01L27/10832 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H01L21/84 , H01L21/845 , H01L27/0629 , H01L27/0733 , H01L27/10826 , H01L27/10829 , H01L27/10858 , H01L27/10867 , H01L27/10879 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/04 , H01L29/0649 , H01L29/517 , H01L29/66181 , H01L29/945
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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公开(公告)号：US20160254150A1
公开(公告)日：2016-09-01
申请号：US14634050
申请日：2015-02-27
发明人： Kevin K. Chan , Marinus J.P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC分类号： H01L21/02 , H01L21/225 , H01L29/207
CPC分类号： H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
摘要： An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
摘要翻译： 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。
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17.发明授权Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer 有权通过氧化富铝底层降低III-V场效应晶体管的短沟道效应公开(公告)号：US08907381B2
公开(公告)日：2014-12-09
申请号：US14027609
申请日：2013-09-16
发明人： Cheng-Wei Cheng , Shu-Jen Han , Masaharu Kobayashi , Ko-Tao Lee , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L21/4763 , H01L29/78
CPC分类号： H01L29/78 , H01L23/485 , H01L29/0847 , H01L29/1083 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/517 , H01L29/66522 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.
摘要翻译： 在一个实施例中，提供了一种形成半导体器件的方法，其可以包括在III-V半导体衬底的沟道部分上形成包括栅极结构的半导体器件。 包含III-V基底层，存在于III-V基底层上的含铝III-V半导体层的III-V半导体衬底和III-V沟道层。 在栅极结构的相对侧上氧化含铝III-V族半导体层的一部分。 在被氧化的含铝III-V族半导体层的部分上形成凸起的源区和升高的漏极区。 与升高的源极区域和升高的漏极区域形成互连。
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18.发明申请REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER 有权通过氧化铝合金底层降低III-V场效应晶体管的短路通道效应公开(公告)号：US20140332855A1
公开(公告)日：2014-11-13
申请号：US13888657
申请日：2013-05-07
发明人： Cheng-Wei Cheng , Shu-Jen Han , Masaharu Kobayashi , Ko-Tao Lee , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L29/20
CPC分类号： H01L29/78 , H01L23/485 , H01L29/0847 , H01L29/1083 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/517 , H01L29/66522 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.
摘要翻译： 在一个实施例中，提供了一种形成半导体器件的方法，其可以包括在III-V半导体衬底的沟道部分上形成包括栅极结构的半导体器件。 包含III-V基底层，存在于III-V基底层上的含铝III-V半导体层的III-V半导体衬底和III-V沟道层。 在栅极结构的相对侧上氧化含铝III-V族半导体层的一部分。 在被氧化的含铝III-V族半导体层的部分上形成凸起的源区和升高的漏极区。 与升高的源极区域和升高的漏极区域形成互连。
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19.发明申请SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 有权具有深度电容电容器的半导体结构及其制造方法公开(公告)号：US20140264522A1
公开(公告)日：2014-09-18
申请号：US13804647
申请日：2013-03-14
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
CPC分类号： H01L27/10832 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H01L21/84 , H01L21/845 , H01L27/0629 , H01L27/0733 , H01L27/10826 , H01L27/10829 , H01L27/10858 , H01L27/10867 , H01L27/10879 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/04 , H01L29/0649 , H01L29/517 , H01L29/66181 , H01L29/945
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
摘要翻译： 公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。 该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。 该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。 该方法还包括在多晶硅鳍片上形成绝缘体层。 该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。
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公开(公告)号：US11056493B2
公开(公告)日：2021-07-06
申请号：US16295505
申请日：2019-03-07
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L27/07 , H01L27/12 , H01L29/94 , H01L21/28 , H01L29/78 , H01L21/84 , H01L29/66 , G06F30/30 , G06F30/39 , G06F30/392 , G06F30/10 , H01L49/02 , H01L29/04 , H01L29/06 , H01L29/51 , H01L27/06
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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