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公开(公告)号：US09721854B2
公开(公告)日：2017-08-01
申请号：US13705213
申请日：2012-12-05
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
CPC classification number: H01L22/14 , G01R31/024 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.
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公开(公告)号：US09380688B1
公开(公告)日：2016-06-28
申请号：US14985542
申请日：2015-12-31
Inventor： Kai D. Feng , Yang Liu , Dongbing Shao , Zheng Xu
CPC classification number: H05F3/04 , H01L23/60 , H01L27/0248 , H01L27/0288
Abstract: Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.
Abstract translation: 方面涉及用于ESD保护的静电放电（ESD）系统和制造方法。 ESD系统包括下基板，设置在包括多个空腔的下基板上的底部填充层，以及设置在底部填充层上的上基板。 上基板包括多个通风轴。 ESD系统还包括设置在底部填充物中的多个空腔内的一个或多个空腔内的多个气隙金属尖端结构，其中多个通气轴与多个气隙金属尖端结构对齐。 至少一个气隙尖端结构包括沿着垂直于基底的垂直轴放置的上金属末端和下金属末端。 在上金属端头和下金属端头之间设有空气腔，形成一个空气室。
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公开(公告)号：US09281236B2
公开(公告)日：2016-03-08
申请号：US14718128
申请日：2015-05-21
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC: H03K19/00 , H01L21/768 , H01L23/535 , H01L23/00 , H03K19/003 , H03K19/0948
CPC classification number: H01L21/76802 , G06F21/73 , G09C1/00 , H01L21/76816 , H01L21/76838 , H01L21/76877 , H01L23/535 , H01L23/564 , H01L23/57 , H01L2924/0002 , H03K19/003 , H03K19/0948 , H04L9/3278 , H04L2209/12 , H01L2924/00
Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.
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公开(公告)号：US09217769B2
公开(公告)日：2015-12-22
申请号：US13647719
申请日：2012-10-09
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Kai D. Feng , Hailing Wang , Zhijian Yang
CPC classification number: G01R31/2824 , H03K3/0315
Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.
Abstract translation: 包括多个反相级的环形振荡器的测试电路包括电源，所述电源被配置为在功率输出时向所述环形振荡器的所述多个反相级提供电压; 以及位于电源的功率输出和环形振荡器的反相级的直流（DC）偏置输入之间的功率感测电阻器，其中来自功率感测电阻器的信号被配置为被监视以确定 环形振荡器。
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公开(公告)号：US20150303191A1
公开(公告)日：2015-10-22
申请号：US14257143
申请日：2014-04-21
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Dan Moy , Chengwen Pei , Robert R. Robison , Pinping Sun , Richard A. Wachnik , Ping-Chuan Wang
CPC classification number: H01L27/0733 , H01L27/0629 , H01L27/0805 , H01L27/11206 , H01L29/66181 , H01L29/945
Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.
Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。
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Patent Agency Ranking
公开(公告)号：US20150255326A1
公开(公告)日：2015-09-10
申请号：US14718128
申请日：2015-05-21
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC: H01L21/768 , H03K19/0948 , H03K19/003
CPC classification number: H01L21/76802 , G06F21/73 , G09C1/00 , H01L21/76816 , H01L21/76838 , H01L21/76877 , H01L23/535 , H01L23/564 , H01L23/57 , H01L2924/0002 , H03K19/003 , H03K19/0948 , H04L9/3278 , H04L2209/12 , H01L2924/00
Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.
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公开(公告)号：US09117824B2
公开(公告)日：2015-08-25
申请号：US14032218
申请日：2013-09-20
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/535 , H01L21/768 , H01L23/00
CPC classification number: H01L21/76802 , G06F21/73 , G09C1/00 , H01L21/76816 , H01L21/76838 , H01L21/76877 , H01L23/535 , H01L23/564 , H01L23/57 , H01L2924/0002 , H03K19/003 , H03K19/0948 , H04L9/3278 , H04L2209/12 , H01L2924/00
Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.
Abstract translation: 本发明的实施例包括一种半导体结构，其包含用于实现物理不可克隆功能（PUF）的线性随机图案化互连结构的后端，用于形成半导体器件的方法以及用于使互连结构实现物理不可克隆功能的电路 。 该方法包括在衬底上形成半导体衬底和介电层。 随机图案化的互连结构形成在电介质层中。 互连结构的随机图案用于实现物理不可克隆功能，并且是在半导体结构的制造期间发生缺陷的结果。 该电路包括n沟道和p沟道金属氧化物半导体场效应晶体管（MOSFET）和随机图案化的互连结构，其作为MOSFET之间的电连接。 MOSFET之间的随机电气连接用于产生用于诸如认证或识别之类目的的唯一密钥。
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18.发明授权Methodology and apparatus for tuning driving current of semiconductor transistors 有权用于调谐半导体晶体管的驱动电流的方法和装置公开(公告)号：US09059204B2
公开(公告)日：2015-06-16
申请号：US14263067
申请日：2014-04-28
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , J. Edwin Hostetter, Jr. , Ping-Chuan Wang , Zhijian Yang
IPC: H01L21/02 , H01L29/66 , H01L21/326 , G01R31/27 , H01L29/78
CPC classification number: H01L29/66477 , G01R31/275 , H01L21/326 , H01L29/7833
Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.
Abstract translation: 用于修复晶体管的方法和装置可以包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极预定时间。 以这种方式，晶体管结构可以被修复或返回以在原始操作特性或附近操作。
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公开(公告)号：US09391014B2
公开(公告)日：2016-07-12
申请号：US14825303
申请日：2015-08-13
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC: H01L23/522 , H01L23/528 , H04L9/32 , H05K1/02
CPC classification number: H01L23/5222 , H01L21/0274 , H01L21/3212 , H01L21/76816 , H01L21/76834 , H01L21/76837 , H01L21/7684 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H05K1/0289 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。
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公开(公告)号：US20160190005A1
公开(公告)日：2016-06-30
申请号：US15060685
申请日：2016-03-04
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC: H01L21/768 , H01L21/027 , H01L21/321
CPC classification number: H01L23/5222 , H01L21/0274 , H01L21/3212 , H01L21/76816 , H01L21/76834 , H01L21/76837 , H01L21/7684 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H05K1/0289 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
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