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公开(公告)号：US10585346B2
公开(公告)日：2020-03-10
申请号：US15819213
申请日：2017-11-21
Inventor： Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
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公开(公告)号：US10394116B2
公开(公告)日：2019-08-27
申请号：US15696505
申请日：2017-09-06
Inventor： Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
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公开(公告)号：US09380688B1
公开(公告)日：2016-06-28
申请号：US14985542
申请日：2015-12-31
Inventor： Kai D. Feng , Yang Liu , Dongbing Shao , Zheng Xu
CPC classification number: H05F3/04 , H01L23/60 , H01L27/0248 , H01L27/0288
Abstract: Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.
Abstract translation: 方面涉及用于ESD保护的静电放电（ESD）系统和制造方法。 ESD系统包括下基板，设置在包括多个空腔的下基板上的底部填充层，以及设置在底部填充层上的上基板。 上基板包括多个通风轴。 ESD系统还包括设置在底部填充物中的多个空腔内的一个或多个空腔内的多个气隙金属尖端结构，其中多个通气轴与多个气隙金属尖端结构对齐。 至少一个气隙尖端结构包括沿着垂直于基底的垂直轴放置的上金属末端和下金属末端。 在上金属端头和下金属端头之间设有空气腔，形成一个空气室。
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公开(公告)号：US12188961B2
公开(公告)日：2025-01-07
申请号：US17876652
申请日：2022-07-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kushagra Sinha , Zheng Xu , Yufei Wu , Myra Ahmad , Nikhilesh C Sahani
Abstract: A testing apparatus and a method for testing an integrated circuit are described. One embodiment of the testing apparatus may comprise a main probe pin configured for electrical testing of a sample, the sample having a terminal pad, and a secondary probe pin configured for contact testing of the main probe pin against the terminal pad. In some embodiments, the testing apparatus may further comprise an indicator circuit electrically connected to the main probe pin and the secondary probe pin. The indicator circuit may output a signal when the main probe pin and the secondary probe pin are in simultaneous electrical engagement with the terminal pad.
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公开(公告)号：US11877524B2
公开(公告)日：2024-01-16
申请号：US17469203
申请日：2021-09-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Juntao Li , Kangguo Cheng , Dexin Kong , Zheng Xu
IPC: H10N70/00
CPC classification number: H10N70/063 , H10N70/826 , H10N70/8833 , H10N70/021
Abstract: Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.
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Patent Agency Ranking
公开(公告)号：US20230144050A1
公开(公告)日：2023-05-11
申请号：US17519924
申请日：2021-11-05
Applicant: International Business Machines Corporation
Inventor： Dexin Kong , Kangguo Cheng , Juntao Li , Zheng Xu
IPC: H01L45/00
CPC classification number: H01L45/1691 , H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/144
Abstract: Semiconductor devices and methods for forming the semiconductor devices are described. An example semiconductor structure can include a substrate including a first electrode. The example semiconductor structure can further include a heater element directly contacting the first electrode in the substrate. The example semiconductor structure a phase change cell directly on the heater element. The sidewalls of the phase change cell can be encapsulated with a spacer. The example semiconductor structure a second electrode directly on the phase change cell and the spacer.
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公开(公告)号：US20220181154A1
公开(公告)日：2022-06-09
申请号：US17677469
申请日：2022-02-22
Applicant: International Business Machines Corporation
Inventor： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC: H01L21/033 , H01L23/528 , H01L21/768 , H01L21/311
Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
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公开(公告)号：US11058337B2
公开(公告)日：2021-07-13
申请号：US15424265
申请日：2017-02-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Qianwen Chen , Huan Hu , Zheng Xu , Xin Zhang
Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.
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公开(公告)号：US10930734B2
公开(公告)日：2021-02-23
申请号：US16174603
申请日：2018-10-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ruqiang Bao , Zhenxing Bi , Kangguo Cheng , Zheng Xu
IPC: H01L29/06 , H01L29/08 , H01L21/762 , H01L21/02
Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
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公开(公告)号：US10915690B2
公开(公告)日：2021-02-09
申请号：US16383326
申请日：2019-04-12
Applicant: International Business Machines Corporation
Inventor： Dongbing Shao , Yongan Xu , Shyng-Tsong Chen , Zheng Xu
IPC: G06F30/30 , G06F30/398
Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.
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