Inline measurement of through-silicon via depth
    2.
    发明授权
    Inline measurement of through-silicon via depth 有权
    通过深度在线测量直通硅

    公开(公告)号:US09059051B2

    公开(公告)日:2015-06-16

    申请号:US13889374

    申请日:2013-05-08

    CPC classification number: H01L22/26 H01L21/304 H01L22/14 H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Abstract translation: 公开了一种通过硅通孔(TSV)电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点,并且第二组电杆电连接以形成第二电容器节点。 测量电容,并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理,使得半导体晶片变薄使得背面与TSV齐平。

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