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公开(公告)号：US20190044044A1
公开(公告)日：2019-02-07
申请号：US15897712
申请日：2018-02-15
申请人： Intel Corporation
发明人： Lester Lampert , Adel A. Elsherbini , James S. Clarke , Jeanette M. Roberts , Ravi Pillarisetty , David J. Michalak , Kanwaljit Singh , Roman Caudillo , Zachary R. Yoscovits , Nicole K. Thomas , Hubert C. George , Stefano Pellerano
摘要： Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.
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公开(公告)号：US20190043989A1
公开(公告)日：2019-02-07
申请号：US16017942
申请日：2018-06-25
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts , James S. Clarke
IPC分类号： H01L29/78 , H01L29/778 , H01L29/66 , H01L23/522 , H01L29/06
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.
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13.发明申请公开(公告)号：US20190043919A1
公开(公告)日：2019-02-07
申请号：US16012815
申请日：2018-06-20
申请人： Intel Corporation
发明人： Hubert C. George , Adel A. Elsherbini , Lester Lampert , James S. Clarke , Ravi Pillarisetty , Zachary R. Yoscovits , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts
摘要： Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.
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公开(公告)号：US20190006572A1
公开(公告)日：2019-01-03
申请号：US15637682
申请日：2017-06-29
申请人： Intel Corporation
发明人： Javier A. Falcon , Adel A. Elsherbini , Johanna M. Swan , Shawna M. Liff , Ye Seul Nam , James S. Clarke , Jeanette M. Roberts , Roman Caudillo
IPC分类号： H01L39/04 , H01L25/16 , H01L23/538 , H01L23/66 , H01L23/552 , H01L39/02 , H01L39/24 , H01P3/08 , H01P11/00 , H05K1/02 , G06N99/00
摘要： Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.
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公开(公告)号：US11450765B2
公开(公告)日：2022-09-20
申请号：US16143676
申请日：2018-09-27
申请人： Intel Corporation
发明人： Hubert C. George , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts
IPC分类号： H01L29/778 , H01L29/51 , H01L29/49 , H01L29/15 , H01L27/02 , H01L29/82 , H01L29/66 , H01L23/538 , G06N10/00
摘要： A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.
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公开(公告)号：US11183564B2
公开(公告)日：2021-11-23
申请号：US16015087
申请日：2018-06-21
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Payam Amin , Roza Kotlyar , Patrick H. Keys , Hubert C. George , Kanwaljit Singh , James S. Clarke , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts
IPC分类号： H01L29/12 , H01L29/66 , H01L29/76 , H01L29/423 , H01L29/165 , H01L27/18 , H01L21/8234 , H01L29/10 , G06N10/00 , H01L39/14 , H01L29/06 , B82Y10/00 , H01L29/82 , H01L29/40 , H01L21/321 , H01L21/02 , H01L29/778 , H01L29/43
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
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公开(公告)号：US11011693B2
公开(公告)日：2021-05-18
申请号：US16450396
申请日：2019-06-24
申请人： Intel Corporation
发明人： Lester Lampert , Ravi Pillarisetty , Nicole K. Thomas , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Thomas Francis Watson , Stephanie A. Bojarski , James S. Clarke
摘要： Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.
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公开(公告)号：US20200373351A1
公开(公告)日：2020-11-26
申请号：US16635193
申请日：2017-09-18
申请人： Intel Corporation
发明人： Jeanette M. Roberts , Wesley T. Harrison , Adel A. Elsherbini , Stefano Pellerano , Zachary R. Yoscovits , Lester Lampert , Ravi Pillarisetty , Roman Caudillo , Hubert C. George , Nicole K. Thomas , David J. Michalak , Kanwaljit Singh , James S. Clarke
摘要： Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.
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公开(公告)号：US20200312989A1
公开(公告)日：2020-10-01
申请号：US16365018
申请日：2019-03-26
申请人： Intel Corporation
发明人： Hubert C. George , Sarah Atanasov , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts , Stephanie A. Bojarski
IPC分类号： H01L29/775 , H01L29/423 , H01L29/78 , H01L29/66 , G06N10/00
摘要： Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.
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公开(公告)号：US20200312963A1
公开(公告)日：2020-10-01
申请号：US16367155
申请日：2019-03-27
申请人： Intel Corporation
发明人： Stephanie A. Bojarski , Hubert C. George , Sarah Atanasov , Nicole K. Thomas , Ravi Pillarisetty , Lester Lampert , Thomas Francis Watson , David J. Michalak , Roman Caudillo , Jeanette M. Roberts , James S. Clarke
IPC分类号： H01L29/12 , H01L29/78 , H01L27/088 , H01L29/66 , G06N10/00 , H01L21/768 , H01L23/522 , H01L23/528
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.
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