公开(公告)号：US08815686B2

公开(公告)日：2014-08-26

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L21/336

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。

公开(公告)号：US10475743B2

公开(公告)日：2019-11-12

申请号：US15458366

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Mueller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

公开(公告)号：US20150262814A1

公开(公告)日：2015-09-17

申请号：US14207685

申请日：2014-03-13

Applicant: Infineon Technologies AG

Inventor： Mathias Plappert ,  Eric Graetz ,  Andreas Behrendt ,  Oliver Humbel ,  Carsten Schaeffer ,  Angelika Koprowski

IPC: H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L23/29 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L21/02126 ,  H01L21/02282 ,  H01L21/02318 ,  H01L23/296 ,  H01L23/3171 ,  H01L23/564 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/66325 ,  H01L29/73 ,  H01L29/7393 ,  H01L2224/04042 ,  H01L2224/4847 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power semiconductor device in accordance with various embodiments may include: a semiconductor body; and a passivation layer disposed over at least a portion of the semiconductor body, wherein the passivation layer includes an organic dielectric material having a water uptake of less than or equal to 0.5 wt % in saturation.

Abstract translation: 根据各种实施例的功率半导体器件可以包括：半导体本体; 以及设置在所述半导体本体的至少一部分上的钝化层，其中所述钝化层包括具有小于或等于饱和度的0.5重量％的吸水率的有机介电材料。

公开(公告)号：US20150179637A1

公开(公告)日：2015-06-25

申请号：US14561357

申请日：2014-12-05

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Carsten Schaeffer

IPC: H01L27/06 ,  H01L29/47 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0615 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.

Abstract translation: 半导体器件包括从半导体衬底的主表面延伸到半导体衬底中的第一掺杂区域。 此外，半导体器件包括邻近第一掺杂区布置的第二掺杂区。 第一掺杂区域包括从半导体衬底的主表面延伸到第二掺杂区域的至少一个低掺杂剂量部分。 第一掺杂区域的低掺杂剂量部分内的掺杂剂量小于击穿电荷的3倍。 另外，半导体器件包括与半导体衬底的主表面处的第一掺杂区域接触的第一电极结构。 第一电极结构在半导体衬底的主表面上的功函数大于4.9eV或低于4.4eV。

公开(公告)号：US20150109050A1

公开(公告)日：2015-04-23

申请号：US14551632

申请日：2014-11-24

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H03K17/66 ,  H03K3/01 ,  H01L29/739

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。

公开(公告)号：US20140015007A1

公开(公告)日：2014-01-16

申请号：US13923436

申请日：2013-06-21

Applicant: Infineon Technologies AG

Inventor： Dorothea Werber ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Carsten Schaeffer ,  Volodymyr Komarnitskyy ,  Anton Mauder ,  Holger Schulze ,  Gerhard Miller

IPC: H01L29/06

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.

Abstract translation: 半导体器件包括具有至少一个器件单元的单元区域，其中至少一个器件单元包括第一导电类型的第一器件区域。 所述半导体器件还包括邻接所述至少一个器件单元的第一器件区域的第二导电类型的漂移区域，与所述漂移区域相邻的所述第一导电类型的掺杂区域以及被配置为减少电荷的电荷载流子寿命降低装置 在第一导电类型的掺杂区域中的载流子寿命。

公开(公告)号：US20130224921A1

公开(公告)日：2013-08-29

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/66

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。

公开(公告)号：US12183696B2

公开(公告)日：2024-12-31

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US11764176B2

公开(公告)日：2023-09-19

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US11139375B2

公开(公告)日：2021-10-05

申请号：US16502451

申请日：2019-07-03

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Alexander Breymesser ,  Bernhard Goller ,  Ronny Kern ,  Matteo Piccin ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L29/16 ,  H01L21/784 ,  H01L21/683 ,  H01L21/04 ,  H01L29/66 ,  H01L23/31 ,  H01L23/00 ,  H01L29/45

Abstract: According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.