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11.发明申请公开(公告)号：US20190253058A1
公开(公告)日：2019-08-15
申请号：US16329312
申请日：2016-09-29
Applicant: INTEL IP CORPORATION
Inventor： Ashoke Ravi , Rotem Banin , Ofir Degani , David Ben-Haim , Yigal Kalmanovich
CPC classification number: H03L7/0995 , H03L7/093 , H03L2207/50 , H04L7/0331 , H04L7/08
Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
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公开(公告)号：US20180175878A1
公开(公告)日：2018-06-21
申请号：US15811721
申请日：2017-11-14
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Sebastian Sievert
CPC classification number: H03M1/82 , H03K5/131 , H03K5/135 , H03K2005/00052 , H03K2005/00058 , H03M1/007 , H04W88/02
Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
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公开(公告)号：US20170085365A1
公开(公告)日：2017-03-23
申请号：US14861132
申请日：2015-09-22
Applicant: Intel IP Corporation
Inventor： Ashoke Ravi , Ofir Degani , Rotem Banin , Assaf Ben-Bassat
CPC classification number: H04L7/042 , G04F10/005 , H03K5/135 , H03M1/1061 , H03M1/82 , H04B1/0475 , H04L7/0054
Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.
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公开(公告)号：US09407245B2
公开(公告)日：2016-08-02
申请号：US14318857
申请日：2014-06-30
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Assaf Ben-Bassat , Ofir Degani , Rotem Banin
IPC: H03K3/027 , H03L7/06 , H03K5/1252 , H03L7/099 , H03L7/081
CPC classification number: H03K5/1252 , H03K5/135 , H03L7/081 , H03L7/0814 , H03L7/0995 , H03L7/0998
Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.
Abstract translation: 此应用程序除了其他内容之外还讨论了数字时间转换器（DTC）的内插器架构。 在一个示例中，内插器可以包括内插单元和配置的保持单元基于至少两个偏移时钟信号提供内插输出。 在某些示例中，示例性内插器可以提供具有改进的抗噪声能力的内插器输出的无竞争力控制。
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公开(公告)号：US11387841B2
公开(公告)日：2022-07-12
申请号：US16650036
申请日：2017-12-15
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Bassam Khamaisi , Gil Asa
Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal.
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Patent Agency Ranking
公开(公告)号：US10768580B2
公开(公告)日：2020-09-08
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US20190384230A1
公开(公告)日：2019-12-19
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US10177774B2
公开(公告)日：2019-01-08
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
IPC: H03M1/66 , H03M1/06 , H03M1/46 , H03M7/42 , H03F3/195 , H03F3/24 , H03M1/68 , H03M1/82 , H03M5/02
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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公开(公告)号：US09923563B1
公开(公告)日：2018-03-20
申请号：US15389520
申请日：2016-12-23
Applicant: Intel IP Corporation
Inventor： Gil Horovitz , Elan Banin , Igal Kushnir , Aryeh Farber , Ran Krichman , Ofir Degani , Rotem Banin
IPC: H03L7/08
CPC classification number: H03L7/08 , H03K5/1565 , H03L7/0805 , H03L7/085 , H03L2207/10
Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.
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公开(公告)号：US20180006658A1
公开(公告)日：2018-01-04
申请号：US15583063
申请日：2017-05-01
Applicant: INTEL IP CORPORATION
Inventor： Georgios Yorgos Palaskas , Paolo Madoglio , Peter Preyler , Rotem Banin
CPC classification number: H03M1/06 , H03F3/195 , H03F3/24 , H03M1/466 , H03M1/68 , H03M1/82 , H03M5/02 , H03M7/42
Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.
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