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    Wafer level fan-out application specific integrated circuit bridge memory stack
    15.
    发明授权
    Wafer level fan-out application specific integrated circuit bridge memory stack 有权

    公开(公告)号：US10930592B2

    公开(公告)日：2021-02-23

    申请号：US16405304

    申请日：2019-05-07

    Applicant: Google LLC

    Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Teckgyu Kang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L49/02 ,  H01L25/16 ,  H01L23/48 ,  H01L23/31

    Abstract: A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.

    INTEGRATED CIRCUIT SUBSTRATE FOR CONTAINING LIQUID ADHESIVE BLEED-OUT
    16.
    发明申请
    INTEGRATED CIRCUIT SUBSTRATE FOR CONTAINING LIQUID ADHESIVE BLEED-OUT 审中-公开

    公开(公告)号：US20200185292A1

    公开(公告)日：2020-06-11

    申请号：US16358203

    申请日：2019-03-19

    Applicant: Google LLC

    Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

    IPC: H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

    Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

    COOLING ELECTRONIC DEVICES IN A DATA CENTER
    17.
    发明申请
    COOLING ELECTRONIC DEVICES IN A DATA CENTER 审中-公开

    公开(公告)号：US20190327859A1

    公开(公告)日：2019-10-24

    申请号：US15957161

    申请日：2018-04-19

    Applicant: Google LLC

    Inventor： Madhusudan Krishnan Iyengar ,  Christopher Gregory Malone ,  Yuan Li ,  Jorge Padilla ,  Woon Seong Kwon ,  Teckgyu Kang ,  Norman Paul Jouppi

    IPC: H05K7/20

    Abstract: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices, the plurality of data center electronic devices including at least one heat generating processor device; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member shaped to thermally contact the heat generating processor device, the heat transfer member including an inlet port and an outlet port that are in fluid communication with a cooling liquid flow path defined through the heat transfer member.

    INTEGRATION OF SILICON PHOTONICS IC FOR HIGH DATA RATE
    18.
    发明申请
    INTEGRATION OF SILICON PHOTONICS IC FOR HIGH DATA RATE 审中-公开

    公开(公告)号：US20180299628A1

    公开(公告)日：2018-10-18

    申请号：US15948435

    申请日：2018-04-09

    Applicant: Google LLC

    Inventor： Hong Liu ,  Ryohei Urata ,  Woon Seong Kwon ,  Teckgyu Kang

    IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H05K3/34 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18

    Abstract: Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.

    Active Silicon D2D Bridge
    20.
    发明公开
    Active Silicon D2D Bridge 审中-公开

    公开(公告)号：US20230411297A1

    公开(公告)日：2023-12-21

    申请号：US17841188

    申请日：2022-06-15

    Applicant: Google LLC

    Inventor： Georgios Konstadinidis ,  Woon-Seong Kwon ,  Jaesik Lee ,  Teckgyu Kang ,  Jin Y. Kim ,  Sukalpa Biswas ,  Biao He ,  Yujeong Shim

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

    CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/5384 ,  H01L23/5385 ,  H01L21/4853 ,  H01L21/486 ,  H01L25/50

    Abstract: A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.

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