公开(公告)号：US06531382B1

公开(公告)日：2003-03-11

申请号：US10140662

申请日：2002-05-08

Applicant: Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

Inventor： Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

IPC: H01L213205

CPC classification number: H01L21/76802 ,  H01L21/76838

Abstract: A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.

Abstract translation: 已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。 首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。 在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。 除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。 原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

公开(公告)号：US20130175653A1

公开(公告)日：2013-07-11

申请号：US13343922

申请日：2012-01-05

Applicant: Shih-Chieh CHANG ,  Yu-Ku LIN ,  Ying-Lang WANG

Inventor： Shih-Chieh CHANG ,  Yu-Ku LIN ,  Ying-Lang WANG

IPC: H01L31/102 ,  H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

Abstract: This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

Abstract translation: 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面的总厚度变化小于约0.15μm。

公开(公告)号：US20130126950A1

公开(公告)日：2013-05-23

申请号：US13304235

申请日：2011-11-23

Applicant: Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

公开(公告)号：US07368379B2

公开(公告)日：2008-05-06

申请号：US11197009

申请日：2005-08-04

Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi S Chern

Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi S Chern

IPC: H01L21/3205

CPC classification number: C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76877

Abstract: An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

Abstract translation: 提供了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

公开(公告)号：US20070152342A1

公开(公告)日：2007-07-05

申请号：US11323484

申请日：2005-12-30

Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

IPC: H01L23/52

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

Abstract translation: 通过半导体产品互连的结构和工艺流程。 提供底部金属层以表示半导体产品中的连接层。 底部金属层上的隔离层包括露出底部金属层的一部分的通孔。 通孔包括侧壁和底部。 第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。 在通孔的底部和第一阻挡金属层上形成金属底层。 在金属底层上形成第二阻挡金属层。 金属填充层填充通孔。 金属底层和第二阻挡金属层之间的晶格失配小于约5％。

公开(公告)号：US20070126120A1

公开(公告)日：2007-06-07

申请号：US11294789

申请日：2005-12-06

Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.

Abstract translation: 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

公开(公告)号：US20070034517A1

公开(公告)日：2007-02-15

申请号：US11197009

申请日：2005-08-04

Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

IPC: B05D5/12 ,  C25D5/02

CPC classification number: C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76877

Abstract: An interconnect structure for a semiconductor device and its method of manufacture is described. The interconnect structure comprises a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

Abstract translation: 描述了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

公开(公告)号：US07128821B2

公开(公告)日：2006-10-31

申请号：US10761477

申请日：2004-01-20

Applicant: Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: C25D5/34 ,  C25F1/00

CPC classification number: H01L21/76843 ,  B24B37/042 ,  B24B37/046 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25F3/02 ,  H01L21/02068 ,  H01L21/32115 ,  H01L21/76865 ,  H01L21/76873

Abstract: An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.

Abstract translation: 公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。 该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。 该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

公开(公告)号：US20060055928A1

公开(公告)日：2006-03-16

申请号：US10942554

申请日：2004-09-15

Applicant: Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

Inventor： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

IPC: G01B11/00

CPC classification number: H01L22/34 ,  G01B21/042

Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Abstract translation: 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时，激光束撞击目标点并释放到生产中。 如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

公开(公告)号：US20050236181A1

公开(公告)日：2005-10-27

申请号：US10917543

申请日：2004-08-12

Applicant: Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

Inventor： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

IPC: H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.

Abstract translation: 公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。 该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。 还公开了具有至少一个无空隙通孔的互连结构。