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    Test device and method for laser alignment calibration
    1.
    发明授权
    Test device and method for laser alignment calibration 有权
    用于激光对准校准的测试装置和方法

    公开(公告)号：US07304728B2

    公开(公告)日：2007-12-04

    申请号：US10942554

    申请日：2004-09-15

    申请人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

    发明人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

    IPC分类号： G01C1/00

    CPC分类号： H01L22/34 ,  G01B21/042

    摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

    摘要翻译： 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时，激光束撞击目标点并释放到生产中。 如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

    Current-leveling electroplating/electropolishing electrode
    2.
    发明申请
    Current-leveling electroplating/electropolishing electrode 有权
    电流调平电镀/电解抛光电极

    公开(公告)号：US20060086609A1

    公开(公告)日：2006-04-27

    申请号：US10971836

    申请日：2004-10-22

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

    IPC分类号： C25B11/02

    CPC分类号： H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

    摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

    摘要翻译： 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

    Oxidation-free copper metallization process using in-situ baking
    4.
    发明授权
    Oxidation-free copper metallization process using in-situ baking 有权
    无氧化铜金属化工艺采用原位烘烤

    公开(公告)号：US08470390B2

    公开(公告)日：2013-06-25

    申请号：US11972785

    申请日：2008-01-11

    申请人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    发明人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    IPC分类号： B05D5/12 ,  C23C14/00

    CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

    Oxidation-Free Copper Metallization Process Using In-situ Baking
    5.
    发明申请
    Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
    使用原位烘烤的无氧铜金属化工艺

    公开(公告)号：US20090181164A1

    公开(公告)日：2009-07-16

    申请号：US11972785

    申请日：2008-01-11

    申请人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    发明人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    IPC分类号： H05K3/46

    CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

    Plating apparatuses and processes
    6.
    发明申请
    Plating apparatuses and processes 审中-公开
    电镀设备和工艺

    公开(公告)号：US20070084730A1

    公开(公告)日：2007-04-19

    申请号：US11248176

    申请日：2005-10-13

    申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： C25D5/48

    CPC分类号： C25D21/00 ,  C25D5/00 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    摘要： Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

    摘要翻译： 电镀设备和电镀工艺。 电镀装置包括电镀站和邻近电镀站的电镀后处理站。 电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。 后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    7.
    发明授权
    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
    在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法

    公开(公告)号：US07071100B2

    公开(公告)日：2006-07-04

    申请号：US10788912

    申请日：2004-02-27

    申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

    摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

    摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

    Copper plating of semiconductor devices using intermediate immersion step
    8.
    发明申请
    Copper plating of semiconductor devices using intermediate immersion step 有权
    使用中间浸渍步骤的半导体器件的镀铜

    公开(公告)号：US20050250327A1

    公开(公告)日：2005-11-10

    申请号：US10840095

    申请日：2004-05-06

    申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    IPC分类号： C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288 ,  H01L21/44

    CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

    摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

    摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    9.
    发明申请
    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
    在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法

    公开(公告)号：US20050191855A1

    公开(公告)日：2005-09-01

    申请号：US10788912

    申请日：2004-02-27

    申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

    摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

    摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。