公开(公告)号：US06258706B1

公开(公告)日：2001-07-10

申请号：US09325038

申请日：1999-06-07

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  J. H. Horng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  J. H. Horng

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract translation: 公开了一种形成具有应力缓冲特性的棋盘图形接合焊盘结构和形成的焊盘结构的方法。 在一种方法中，首先在硅衬底的表面中形成多个场氧化物区域。 然后在衬底上沉积并形成导电层，例如多晶硅化物，以形成台阶表面，随后将金属层沉积在导电层的顶部上以形成接合焊盘。 在金属层上再现的阶梯结构用于在引线接合工艺期间分配结合应力，从而基本消除接合焊盘剥离缺陷。 在另一种方法中，导电层首先形成为具有随后形成的绝缘侧壁的导电栅极。 可以获得类似的金属层上的台阶表面，以实现新方法的应力缓冲特性。

公开(公告)号：US06251724B1

公开(公告)日：2001-06-26

申请号：US09431235

申请日：1999-11-01

Applicant: Shu-Mei Ku ,  Lin-June Wu

Inventor： Shu-Mei Ku ,  Lin-June Wu

IPC: H01L218242

CPC classification number: H01L27/0629 ,  H01L27/1085 ,  H01L27/10894

Abstract: A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removing the silicon nitride, H2 can penetrate to the polysilicon and thereby increase the uniformity of the VT. In a first embodiment of the invention, the silicon nitride capacitor dielectric layer is etched away from over the poly-1 layer in the pad area. The removal of the SiN layer allows H2 to penetrate into the poly-1 layer and improve the threshold voltage (VT). Uniformity of long channel VT-N was improved when we modify the pad struture of PCM to increase the clear out ratio of capacitor Si3N4 to 1.0584%. In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the process control monitor (PCM) testsite area between the chips. In a third embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the scribe area between the between the chips.

Abstract translation: 一种在包括诸如焊盘接触区域，过程控制监视器（PCM）现场区域和划线区域之类的非电容器区域的晶片的部分上从多晶硅层上方去除氮化硅电容器电介质层的方法。 通过去除氮化硅，H2可以渗透到多晶硅，从而增加VT的均匀性。 在本发明的第一实施例中，氮化硅电容器介质层被蚀刻远离焊盘区域中的多晶硅层1。 去除SiN层允许H 2渗透到poly-1层中并提高阈值电压（VT）。 当改变PCM的焊盘结构以增加电容器Si3N4的清除比达到1.0584％时，长沟道VT-N的均匀性得到改善。 在本发明的第二实施例中，在芯片之间的过程控制监视器（PCM）测试点区域中，氮化硅电容器电介质被蚀刻远离多晶硅层1。 在本发明的第三实施例中，在芯片之间的划线区域中的氮化硅电容器电介质被蚀刻远离多晶硅层。

公开(公告)号：US5942800A

公开(公告)日：1999-08-24

申请号：US102309

申请日：1998-06-22

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  Jan-Her Horng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  Jan-Her Horng

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L24/45 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043

Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract translation: 公开了一种形成具有应力缓冲特性的棋盘图形接合焊盘结构和形成的焊盘结构的方法。 在一种方法中，首先在硅衬底的表面中形成多个场氧化物区域。 然后在衬底上沉积并形成导电层，例如多晶硅化物，以形成台阶表面，随后将金属层沉积在导电层的顶部上以形成接合焊盘。 在金属层上再现的阶梯结构用于在引线接合工艺期间分配结合应力，从而基本消除接合焊盘剥离缺陷。 在另一种方法中，导电层首先形成为具有随后形成的绝缘侧壁的导电栅极。 可以获得类似的金属层上的台阶表面，以实现新方法的应力缓冲特性。

公开(公告)号：US20110024866A1

公开(公告)日：2011-02-03

申请号：US12511789

申请日：2009-07-29

Applicant: Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

Inventor： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC: H01L31/02 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/1464 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract translation: 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成了称为“大通孔”的较大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

Abstract translation: 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

公开(公告)号：US06180964B2

公开(公告)日：2001-01-30

申请号：US09205112

申请日：1998-12-03

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  T. Cheng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  T. Cheng

IPC: H01L2974

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/85399 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An improved bond pad structure for semiconductor devices provides improved electrical isolation between adjacent bond pads by incorporating a pair of pn junctions between the pad and substrate. The pn junctions are defined by a first well of either P of N type material, formed within a substrate, and a second well or region of a P or N type material formed wholly within the first well. A bond wire is secured to an upper surface of the second region such that the wire, first and second regions and substrate are connected in electrical series relationship and provide an equivalent circuit of two series connected diodes reversed in polarity so as to block both negative and positive components of an applied voltage, thus providing electrical isolation for the bond pad structure.

Abstract translation: 用于半导体器件的改进的接合焊盘结构通过在焊盘和衬底之间并入一对pn结来提供相邻接合焊盘之间的改善的电隔离。 pn结由在衬底内形成的N型材料的P的第一阱和完全在第一阱内形成的P或N型材料的第二阱或区域限定。 接合线被固定到第二区域的上表面，使得电线，第一和第二区域和衬底以电串联连接并且提供两个串联连接的二极管极性反转的等效电路，以阻止负极和 施加电压的正分量，从而为接合焊盘结构提供电隔离。

公开(公告)号：US08502335B2

公开(公告)日：2013-08-06

申请号：US12616652

申请日：2009-11-11

Applicant: Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

Inventor： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC: H01L31/00

CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract translation: 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成了称为“大通孔”的较大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US20110024867A1

公开(公告)日：2011-02-03

申请号：US12616652

申请日：2009-11-11

Applicant: Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

Inventor： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC: H01L31/02

CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract translation: 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成了称为“大通孔”的较大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US07220650B2

公开(公告)日：2007-05-22

申请号：US10821438

申请日：2004-04-09

Applicant: Rong-Hui Kao ,  Chang-Sheng Tsao ,  Yen-Ming Chen ,  Lin-June Wu

Inventor： Rong-Hui Kao ,  Chang-Sheng Tsao ,  Yen-Ming Chen ,  Lin-June Wu

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656

Abstract: An offset spacer layer for an LDD ion implantation process is formed by blanket deposition without photolithography and dry etch processes. The offset spacer layer remaining on LDD regions during an ion implantation process prevents a substrate from silicon loss and dosage contamination and has densified characteristics to improve device reliability.

Abstract translation: 用于LDD离子注入工艺的偏移间隔层通过无光刻和干蚀刻工艺的覆盖沉积形成。 在离子注入工艺期间残留在LDD区域上的偏移间隔层防止了衬底的硅损耗和剂量污染，并具有致密的特性以提高器件的可靠性。

公开(公告)号：US20050227446A1

公开(公告)日：2005-10-13

申请号：US10821438

申请日：2004-04-09

Applicant: Rong-Hui Kao ,  Chang-Sheng Tsao ,  Yen-Ming Chen ,  Lin-June Wu

Inventor： Rong-Hui Kao ,  Chang-Sheng Tsao ,  Yen-Ming Chen ,  Lin-June Wu

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/105 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656

Abstract: An offset spacer layer for an LDD ion implantation process is formed by blanket deposition without photolithography and dry etch processes. The offset spacer layer remaining on LDD regions during an ion implantation process prevents a substrate from silicon loss and dosage contamination and has densified characteristics to improve device reliability.

Abstract translation: 用于LDD离子注入工艺的偏移间隔层通过无光刻和干蚀刻工艺的覆盖沉积形成。 在离子注入工艺期间残留在LDD区域上的偏移间隔层防止了衬底的硅损耗和剂量污染，并具有致密的特性以提高器件的可靠性。