公开(公告)号：US06180964B2

公开(公告)日：2001-01-30

申请号：US09205112

申请日：1998-12-03

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  T. Cheng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  T. Cheng

IPC: H01L2974

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/85399 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An improved bond pad structure for semiconductor devices provides improved electrical isolation between adjacent bond pads by incorporating a pair of pn junctions between the pad and substrate. The pn junctions are defined by a first well of either P of N type material, formed within a substrate, and a second well or region of a P or N type material formed wholly within the first well. A bond wire is secured to an upper surface of the second region such that the wire, first and second regions and substrate are connected in electrical series relationship and provide an equivalent circuit of two series connected diodes reversed in polarity so as to block both negative and positive components of an applied voltage, thus providing electrical isolation for the bond pad structure.

Abstract translation: 用于半导体器件的改进的接合焊盘结构通过在焊盘和衬底之间并入一对pn结来提供相邻接合焊盘之间的改善的电隔离。 pn结由在衬底内形成的N型材料的P的第一阱和完全在第一阱内形成的P或N型材料的第二阱或区域限定。 接合线被固定到第二区域的上表面，使得电线，第一和第二区域和衬底以电串联连接并且提供两个串联连接的二极管极性反转的等效电路，以阻止负极和 施加电压的正分量，从而为接合焊盘结构提供电隔离。

公开(公告)号：US06284557B1

公开(公告)日：2001-09-04

申请号：US09414928

申请日：1999-10-12

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L2100

CPC classification number: H01L31/0352 ,  H01L31/102 ,  Y10S438/979

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06693317B2

公开(公告)日：2004-02-17

申请号：US10437147

申请日：2003-05-13

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L2976

CPC classification number: H01L31/101 ,  H01L31/18

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06582981B2

公开(公告)日：2003-06-24

申请号：US09904138

申请日：2001-07-13

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L3118

CPC classification number: H01L31/0352 ,  H01L31/102 ,  Y10S438/979

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06258706B1

公开(公告)日：2001-07-10

申请号：US09325038

申请日：1999-06-07

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  J. H. Horng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  J. H. Horng

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract translation: 公开了一种形成具有应力缓冲特性的棋盘图形接合焊盘结构和形成的焊盘结构的方法。 在一种方法中，首先在硅衬底的表面中形成多个场氧化物区域。 然后在衬底上沉积并形成导电层，例如多晶硅化物，以形成台阶表面，随后将金属层沉积在导电层的顶部上以形成接合焊盘。 在金属层上再现的阶梯结构用于在引线接合工艺期间分配结合应力，从而基本消除接合焊盘剥离缺陷。 在另一种方法中，导电层首先形成为具有随后形成的绝缘侧壁的导电栅极。 可以获得类似的金属层上的台阶表面，以实现新方法的应力缓冲特性。

公开(公告)号：US5942800A

公开(公告)日：1999-08-24

申请号：US102309

申请日：1998-06-22

Applicant: Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  Jan-Her Horng

Inventor： Ho-Yin Yiu ,  Lin-June Wu ,  Bor-Cheng Chen ,  Jan-Her Horng

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L24/45 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043

Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

Abstract translation: 公开了一种形成具有应力缓冲特性的棋盘图形接合焊盘结构和形成的焊盘结构的方法。 在一种方法中，首先在硅衬底的表面中形成多个场氧化物区域。 然后在衬底上沉积并形成导电层，例如多晶硅化物，以形成台阶表面，随后将金属层沉积在导电层的顶部上以形成接合焊盘。 在金属层上再现的阶梯结构用于在引线接合工艺期间分配结合应力，从而基本消除接合焊盘剥离缺陷。 在另一种方法中，导电层首先形成为具有随后形成的绝缘侧壁的导电栅极。 可以获得类似的金属层上的台阶表面，以实现新方法的应力缓冲特性。

公开(公告)号：US08614488B2

公开(公告)日：2013-12-24

申请号：US13314114

申请日：2011-12-07

Applicant: Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

Inventor： Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

IPC: H01L21/70

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/02372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/11002 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

Abstract translation: 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。

公开(公告)号：US20060208360A1

公开(公告)日：2006-09-21

申请号：US11081704

申请日：2005-03-17

Applicant: Ho-Yin Yiu ,  Fu-Jier Fan ,  Yu-Jui Wu ,  Aaron Wang ,  Hsiang-Wei Wang ,  Huang-Sheng Lin ,  Ming-Hsien Chen ,  Ruey-Yun Shiue

Inventor： Ho-Yin Yiu ,  Fu-Jier Fan ,  Yu-Jui Wu ,  Aaron Wang ,  Hsiang-Wei Wang ,  Huang-Sheng Lin ,  Ming-Hsien Chen ,  Ruey-Yun Shiue

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Abstract translation: 用于接合焊盘结构的顶部通孔图案具有至少一个彼此相邻的第一通孔组和至少一个第二通孔组。 第一通孔组具有沿第一方向延伸的至少两条线通孔。 第二通孔组具有沿与第一方向不同的第二方向延伸的至少两条线通孔。 第一通孔组的通路不穿过第二通路组的通路。

公开(公告)号：US08643070B2

公开(公告)日：2014-02-04

申请号：US13314122

申请日：2011-12-07

Applicant: Shu-Ming Chang ,  Chien-Hui Chen ,  Yen-Shih Ho ,  Chien-Hung Liu ,  Ho-Yin Yiu ,  Ying-Nan Wen

Inventor： Shu-Ming Chang ,  Chien-Hui Chen ,  Yen-Shih Ho ,  Chien-Hung Liu ,  Ho-Yin Yiu ,  Ying-Nan Wen

IPC: H01L29/76

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 位于半导体衬底中的漏区; 源区域，位于所述半导体衬底中; 位于所述半导体衬底上或者至少部分地埋在所述半导体衬底中的栅极，其中栅极电介质层位于所述栅极和所述半导体衬底之间; 漏极导电结构，设置在所述半导体衬底的所述第一表面上并电连接到所述漏极区; 源极导电结构，其设置在所述半导体衬底的所述第二表面上并电连接到所述源极区; 以及栅极导电结构，其设置在所述半导体衬底的所述第一表面上并电连接到所述栅极。

公开(公告)号：US07323784B2

公开(公告)日：2008-01-29

申请号：US11081704

申请日：2005-03-17

Applicant: Ho-Yin Yiu ,  Fu-Jier Fan ,  Yu-Jui Wu ,  Aaron Wang ,  Hsiang-Wei Wang ,  Huang-Sheng Lin ,  Ming-Hsien Chen ,  Ruey-Yun Shiue

Inventor： Ho-Yin Yiu ,  Fu-Jier Fan ,  Yu-Jui Wu ,  Aaron Wang ,  Hsiang-Wei Wang ,  Huang-Sheng Lin ,  Ming-Hsien Chen ,  Ruey-Yun Shiue

IPC: H01L29/40

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Abstract translation: 用于接合焊盘结构的顶部通孔图案具有至少一个彼此相邻的第一通孔组和至少一个第二通孔组。 第一通孔组具有沿第一方向延伸的至少两条线通孔。 第二通孔组具有沿与第一方向不同的第二方向延伸的至少两条线通孔。 第一通孔组的通路不穿过第二通路组的通路。