公开(公告)号：US06284557B1

公开(公告)日：2001-09-04

申请号：US09414928

申请日：1999-10-12

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L2100

CPC classification number: H01L31/0352 ,  H01L31/102 ,  Y10S438/979

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06582981B2

公开(公告)日：2003-06-24

申请号：US09904138

申请日：2001-07-13

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L3118

CPC classification number: H01L31/0352 ,  H01L31/102 ,  Y10S438/979

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06693317B2

公开(公告)日：2004-02-17

申请号：US10437147

申请日：2003-05-13

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L2976

CPC classification number: H01L31/101 ,  H01L31/18

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06362491B1

公开(公告)日：2002-03-26

申请号：US09409876

申请日：1999-10-01

Applicant: Jen-Pan Wang ,  Lin-June Wu

Inventor： Jen-Pan Wang ,  Lin-June Wu

IPC: G01B1100

CPC classification number: G03F7/70633 ,  G03F7/70475

Abstract: A method of determining overlay accuracy, using visual inspection, of a first circuit pattern relative to a second circuit pattern. The first circuit pattern and the second circuit pattern are too large to be contained in a single reticle and are formed separately on an integrated circuit wafer and photo stitched together. A first overlay pattern is located adjacent to the first circuit pattern on a mask. A second overlay pattern is located adjacent to the second circuit pattern on a mask, preferably, but not necessarily, the same mask. The first overlay pattern and the second overlay pattern are located so that their images in the layer of developed photoresist will be adjacent to each other after the photoresist is exposed with the first and second circuit patterns and developed. Visual observation of the images of the first and second overlay patterns is then used to determine the overlay accuracy of the first circuit pattern relative to the second circuit pattern.

Abstract translation: 使用目视检查相对于第二电路图案的第一电路图案的覆盖精度的方法。 第一电路图案和第二电路图案太大而不能包含在单个掩模版中，并且分别形成在集成电路晶片上并且被照相缝合在一起。 第一覆盖图案位于与掩模上的第一电路图案相邻的位置。 第二覆盖图案位于掩模附近的第二电路图案附近，优选但不一定是相同的掩模。 第一覆盖图案和第二覆盖图案被定位成使得它们在显影的光致抗蚀剂层中的图像将在用第一和第二电路图案曝光光致抗蚀剂并显影之后彼此相邻。 然后使用第一和第二覆盖图案的图像的视觉观察来确定第一电路图案相对于第二电路图案的覆盖精度。

公开(公告)号：US20130244139A1

公开(公告)日：2013-09-19

申请号：US13421113

申请日：2012-03-15

Applicant: Chien-Hsuan Liu ,  Jen-Pan Wang

Inventor： Chien-Hsuan Liu ,  Jen-Pan Wang

IPC: G03F1/52 ,  G03F7/20 ,  G03B27/54

CPC classification number: G03F1/52 ,  G03F1/24 ,  G03F1/50 ,  G03F1/76 ,  G03F7/70058 ,  G03F7/70283 ,  G03F7/703

Abstract: Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.

Abstract translation: 公开了各种非平面反射光刻掩模，使用这种光刻掩模的系统和方法。 一个实施例是包括透明基板，反射材料和掩模版图案的光刻掩模。 透明基板包括弯曲表面。 反射材料与透明基板的弯曲表面相邻，并且反射材料和透明基板之间的界面是反射表面。 标线图案位于透明基板的第二表面上。 标线图案的反射率小于反射材料的反射率。 公开了形成类似光刻掩模和使用类似光刻掩模的方法。

公开(公告)号：US08962353B2

公开(公告)日：2015-02-24

申请号：US13234964

申请日：2011-09-16

Applicant: Jen-Pan Wang ,  Chao-Chi Chen ,  Yaling Huang

Inventor： Jen-Pan Wang ,  Chao-Chi Chen ,  Yaling Huang

IPC: H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.

Abstract translation: 用于在处理过程中预测半导体器件性能标准的方法和系统。 描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。 描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

公开(公告)号：US08648341B2

公开(公告)日：2014-02-11

申请号：US13403880

申请日：2012-02-23

Applicant: Chung-Yuan Yang ,  Jen-Pan Wang ,  Jiun-Jie Huang

Inventor： Chung-Yuan Yang ,  Jen-Pan Wang ,  Jiun-Jie Huang

IPC: H01L23/58

CPC classification number: H01L22/32 ,  H01L22/34

Abstract: Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.

Abstract translation: 公开了在模具的多层内共享测试功能块之间的测试焊盘的方法和装置。 半导体晶片包括由划线分开的第一管芯和第二管芯。 第一垫，第二垫和第三垫位于划线中。 测试垫也可以位于模具内。 第一焊盘和第二焊盘用于测试第一层内的第一功能块，并且第一焊盘和第三焊盘用于测试第一裸片的第二层内的第二功能块。 共享的第一个测试焊盘用于测试包含在芯片的不同层中的多个功能块。 因此，需要更少的测试焊盘，这导致晶片中划线的面积减小。

公开(公告)号：US20130221353A1

公开(公告)日：2013-08-29

申请号：US13403880

申请日：2012-02-23

Applicant: Chung-Yuan Yang ,  Jen-Pan Wang ,  Jiun-Jie Huang

Inventor： Chung-Yuan Yang ,  Jen-Pan Wang ,  Jiun-Jie Huang

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34

Abstract: Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.

Abstract translation: 公开了在模具的多层内共享测试功能块之间的测试焊盘的方法和装置。 半导体晶片包括由划线分开的第一管芯和第二管芯。 第一垫，第二垫和第三垫位于划线中。 测试垫也可以位于模具内。 第一焊盘和第二焊盘用于测试第一层内的第一功能块，并且第一焊盘和第三焊盘用于测试第一裸片的第二层内的第二功能块。 共享的第一个测试焊盘用于测试包含在芯片的不同层中的多个功能块。 因此，需要更少的测试焊盘，这导致晶片中划线的面积减小。

公开(公告)号：US20130071957A1

公开(公告)日：2013-03-21

申请号：US13234964

申请日：2011-09-16

Applicant: Jen-Pan Wang ,  Chao-Chi Chen ,  Yaling Huang

Inventor： Jen-Pan Wang ,  Chao-Chi Chen ,  Yaling Huang

IPC: H01L21/66

CPC classification number: H01L22/20 ,  H01L22/12

Abstract: Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.

Abstract translation: 用于在处理过程中预测半导体器件性能标准的方法和系统。 描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。 描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

公开(公告)号：US09281246B2

公开(公告)日：2016-03-08

申请号：US13551413

申请日：2012-07-17

Applicant: Yi-Wen Wang ,  Jen-Pan Wang

Inventor： Yi-Wen Wang ,  Jen-Pan Wang

IPC: H01L21/338 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is etched to reduce a thickness of the gate spacer. A strained layer is then formed. The strained layer includes a portion on an outer sidewall of the gate spacer, and a portion over the gate stack.

Abstract translation: 一种方法包括在半导体衬底上形成栅极叠层，并且在栅叠层的侧壁上形成栅极间隔物。 在形成栅极间隔物的步骤之后，蚀刻栅极间隔物以减小栅极间隔物的厚度。 然后形成应变层。 应变层包括栅极间隔物的外侧壁上的部分和栅极堆叠上的部分。