Invention Grant
- Patent Title: Methods and apparatus for testing pads on wafers
- Patent Title (中): 在晶片上测试垫的方法和设备
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Application No.: US13403880Application Date: 2012-02-23
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Publication No.: US08648341B2Publication Date: 2014-02-11
- Inventor: Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
- Applicant: Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.
Public/Granted literature
- US20130221353A1 Methods and Apparatus for Testing Pads on Wafers Public/Granted day:2013-08-29
Information query
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