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    Nonvolatile semiconductor memory device
    12.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07099199B2

    公开(公告)日：2006-08-29

    申请号：US10837593

    申请日：2004-05-04

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

    摘要翻译： 一种非易失性存储装置，包括多个存储器，其中一个是诸如闪存EEPROM的非易失性存储器，其能够从包括擦除操作的装置的处理单元指定多个操作，所述非易失性存储器中的擦除操作执行阈值 电压移动操作和验证操作，并且非易失性存储器能够在擦除操作期间释放I / O总线，从而允许访问其他存储器和/或系统组件。 例如，在擦除操作期间，闪存EEPROM能够释放I / O数据终端，使得EEPROM与CPU电隔离。 CPU然后能够执行系统总线的数据处理，其中可以在诸如ROM和RAM等其他存储器之间传输/接收信息，否则可以与I / O端口进行数据处理。

    Method for designing semiconductor integrated circuit and automatic designing device
    14.
    发明授权
    Method for designing semiconductor integrated circuit and automatic designing device 失效
    半导体集成电路设计方法及自动设计装置

    公开(公告)号：US06845349B1

    公开(公告)日：2005-01-18

    申请号：US09659735

    申请日：2000-09-11

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  G06G7/62

    CPC分类号： H03K19/1737 ,  G06F17/505 ,  H03K19/1736

    摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

    摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

    Nonvolatile semiconductor memory device
    15.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06791882B2

    公开(公告)日：2004-09-14

    申请号：US10175958

    申请日：2002-06-21

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C1604

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

    摘要翻译： 一种具有擦除控制电路的EEPROM，该擦除控制电路在与之相关的擦除操作之后至少对相应的存储单元执行一次读出操作。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反极性的擦除电压施加到控制栅电极 。

    Method for designing semiconductor integrated circuit and automatic designing device
    16.
    发明授权
    Method for designing semiconductor integrated circuit and automatic designing device 失效
    半导体集成电路设计方法及自动设计装置

    公开(公告)号：US06260185B1

    公开(公告)日：2001-07-10

    申请号：US08930219

    申请日：1997-10-20

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06G748

    CPC分类号： G06F17/505 ,  H03K19/1736 ,  H03K19/1737

    摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

    摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

    Nonvolatile semiconductor memory device
    17.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5991200A

    公开(公告)日：1999-11-23

    申请号：US470212

    申请日：1995-06-06

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    18.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5949715A

    公开(公告)日：1999-09-07

    申请号：US720007

    申请日：1996-09-27

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Thin slab continuous casting machine and method
    20.
    发明授权
    Thin slab continuous casting machine and method 失效
    薄板坯连铸机及方法

    公开(公告)号：US5630467A

    公开(公告)日：1997-05-20

    申请号：US536259

    申请日：1995-09-29

    申请人： Yasutsugu Yoshimura ,  Mituru Onose ,  Kenji Horii ,  Koichi Seki ,  Tadashi Nishino ,  Hironori Shimogama ,  Chukichi Hanzawa

    发明人： Yasutsugu Yoshimura ,  Mituru Onose ,  Kenji Horii ,  Koichi Seki ,  Tadashi Nishino ,  Hironori Shimogama ,  Chukichi Hanzawa

    IPC分类号： B21B1/46 ,  B21B31/02 ,  B22D11/12 ,  B22D11/124 ,  B22D11/22 ,  B22D11/20

    CPC分类号： B22D11/1213 ,  B21B1/463 ,  B21B31/02

    摘要： Guide roller units are made movable back and forth in the direction of thickness of a slab, allowing slab lagging covers to be inserted to and withdrawn from gaps formed between the guide roller units and the slab. Depending on the casting speed, those ones of the guide roller units and the slab lagging covers which are in proper positions are replaced from one to the other for selective use so that the respective lengths of a cooling zone and a heat keeping zone are adjusted to control the cooling rate of the slab in a positive manner. The slab temperature can be kept at a value capable of carrying out rolling regardless of change in the casting speed depending on variations in the amount of molten steel supplied.

    摘要翻译： 引导辊单元可在板坯的厚度方向上来回移动，允许板坯滞留盖被插入到引导辊单元和板之间形成的间隙中并从中取出。 取决于铸造速度，那些位于适当位置的导向辊单元和板坯滞留盖被替换为选择性使用，使得冷却区和保温区的各自长度被调整为 以积极的方式控制板坯的冷却速度。 不管根据供给的钢水量的变化，铸造速度的变化，能够将板坯温度保持在能够进行轧制的值。