公开(公告)号：US20090168493A1

公开(公告)日：2009-07-02

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00 ,  H01L21/00 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07473963B2

公开(公告)日：2009-01-06

申请号：US11854734

申请日：2007-09-13

申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

公开(公告)号：US07442987B2

公开(公告)日：2008-10-28

申请号：US12014276

申请日：2008-01-15

申请人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

摘要翻译： 半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。 该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层， 第一和第二电荷存储层。 栅电极远离基板延伸超过第一和第二电荷存储层。 该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。 还讨论了相关的制造方法。

公开(公告)号：US20080185668A1

公开(公告)日：2008-08-07

申请号：US12007819

申请日：2008-01-16

申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

IPC分类号： H01L29/84 ,  H01L21/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

公开(公告)号：US07402483B2

公开(公告)日：2008-07-22

申请号：US11190695

申请日：2005-07-26

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66772

摘要： A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.

摘要翻译： 可以通过在包括沟道层和介于沟道层之间的沟道间层的衬底上形成层叠结构来形成多桥沟MOSFET（MBCFET）。 通过选择性地蚀刻堆叠结构形成沟槽。 沟槽横跨层叠结构彼此平行地延伸，并且将包括通道图案和沟道间图案的第一堆叠部分与第二堆叠部分分开，包括残留在第一堆叠部分两侧的通道和通道间层。 使用选择性外延生长生长第一源区和漏区。 第一源极和漏极区域填充沟槽并连接到由第二堆叠部分限定的第二源极和漏极区域。 选择性地暴露第一堆叠部分的通道间图案的边缘部分。 通过从暴露的边缘部分开始选择性地去除第一堆叠部分的通道间图案，形成通道。 穿通隧道被第一源极和漏极区域以及沟道图案包围。 栅极与栅极电介质层一起形成，栅极填充通孔并延伸到第一堆叠部分上。

公开(公告)号：US20080144364A1

公开(公告)日：2008-06-19

申请号：US12002668

申请日：2007-12-18

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： G11C11/50 ,  H01L21/00

CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

摘要： There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件以及制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线，并且在 第一个方向 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

公开(公告)号：US20080093628A1

公开(公告)日：2008-04-24

申请号：US11941656

申请日：2007-11-16

申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

IPC分类号： H01L29/778

CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 一个门包围有源通道模式并填充隧道。 还公开了相关的中间结构。

公开(公告)号：US07316968B2

公开(公告)日：2008-01-08

申请号：US10974410

申请日：2004-10-27

申请人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

发明人： Sung-Young Lee ,  Sung-Min Kim ,  Dong-Gun Park ,  Chang-Woo Oh ,  Eun-Jung Yun

IPC分类号： H01L21/00

CPC分类号： H01L29/66484 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696

摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

摘要翻译： 在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。 交替层叠栅极层和沟道层。 在初步活性图案上形成硬掩模。 使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。 蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。 源极/漏极层形成在有源沟道图案和表面的暴露侧面上。 选择性地蚀刻栅极层以形成隧道。 门将包围活动通道模式并填充隧道。 还公开了相关的中间结构。

公开(公告)号：US20070200178A1

公开(公告)日：2007-08-30

申请号：US11783518

申请日：2007-04-10

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L27/12

CPC分类号： H01L29/66553 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/7831

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

公开(公告)号：US07253060B2

公开(公告)日：2007-08-07

申请号：US11074711

申请日：2005-03-09

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78654

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

摘要翻译： 栅极全能（GAA）晶体管器件具有一对支柱，其包括源极/漏极区域，桥接源极/漏极区域的沟道区域以及围绕沟道区域的栅极电极和栅极氧化物。 支柱通过提供单晶硅衬底形成，蚀刻衬底以形成一对隔开的沟槽，使得单晶硅的壁站立在沟槽之间，用绝缘材料填充沟槽，将杂质注入 单晶硅的壁，并且在壁中形成开口，使得壁的一部分保持为支柱。 牺牲层形成在开口的底部。 然后，通道区域形成在支柱之间的牺牲层的顶部。 随后去除牺牲层，并且在沟道区周围形成栅极氧化物和栅电极。 使用一个或多个侧壁间隔物来建立沟道区域的有效宽度和/或最小化源极/漏极区域和栅电极之间的寄生电容。