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    Semiconductor Devices
    5.
    发明申请
    Semiconductor Devices 有权
    半导体器件

    公开(公告)号：US20110300693A1

    公开(公告)日：2011-12-08

    申请号：US13207832

    申请日：2011-08-11

    Applicant: Chang-woo Oh

    Inventor： Chang-woo Oh

    IPC: H01L21/20

    CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

    Abstract translation: 提供一种半导体器件。 半导体器件包括半导体衬底，半导体衬底上的第一隔离电介质图案和第一隔离电介质图案上的有源图案。 在半导体衬底和第一隔离电介质图案之间插入半导体图案，并且在半导体衬底和半导体图案之间插入第二隔离电介质图案。 半导体衬底和半导体图案通过连接图案电连接。

    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions
    6.
    发明申请
    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions 审中-公开
    金属氧化物半导体场效应晶体管（MOSFET）包括嵌入式通道区域

    公开(公告)号：US20110079831A1

    公开(公告)日：2011-04-07

    申请号：US12966362

    申请日：2010-12-13

    Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    IPC: H01L29/772

    CPC classification number: H01L29/66583 ,  H01L29/1037 ,  H01L29/66651

    Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

    Abstract translation: 金属氧化物半导体（MOS）晶体管的单位电池在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。

    Semiconductor devices including channel and junction regions of different semiconductor materials
    7.
    发明授权
    Semiconductor devices including channel and junction regions of different semiconductor materials 有权
    半导体器件包括不同半导体材料的沟道和结区

    公开(公告)号：US07859064B1

    公开(公告)日：2010-12-28

    申请号：US11849577

    申请日：2007-09-04

    Applicant: Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    Inventor： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC: H01L29/41

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    Abstract translation: 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    SEMICONDUCTOR DEVICES
    9.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开
    半导体器件

    公开(公告)号：US20100117152A1

    公开(公告)日：2010-05-13

    申请号：US12687286

    申请日：2010-01-14

    Applicant: Chang-Woo Oh

    Inventor： Chang-Woo Oh

    IPC: H01L29/786 ,  H01L21/336

    CPC classification number: H01L27/1203 ,  H01L27/1207 ,  H01L29/7841 ,  H01L29/7851

    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

    Abstract translation: 提供一种半导体器件。 半导体器件包括半导体衬底，半导体衬底上的第一隔离电介质图案和第一隔离电介质图案上的有源图案。 在半导体衬底和第一隔离电介质图案之间插入半导体图案，并且在半导体衬底和半导体图案之间插入第二隔离电介质图案。 半导体衬底和半导体图案通过连接图案电连接。

    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
    10.
    发明申请
    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same 有权
    具有增加的源极/漏极接触面积的垂直沟道鳍效应晶体管及其制造方法

    公开(公告)号：US20100044784A1

    公开(公告)日：2010-02-25

    申请号：US12613025

    申请日：2009-11-05

    Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    Abstract: A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    Abstract translation: 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

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