公开(公告)号：US20230385224A1

公开(公告)日：2023-11-30

申请号：US18137594

申请日：2023-04-21

申请人： Etron Technology, Inc.

发明人： Richard Dewitt Crisp

IPC分类号： G06F13/42 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10 ,  G06F13/28 ,  G06F13/40 ,  G11C8/18

CPC分类号： G06F13/4234 ,  G11C5/025 ,  G11C5/066 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/1072 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G11C8/18

摘要： A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

公开(公告)号：US11798613B2

公开(公告)日：2023-10-24

申请号：US17224878

申请日：2021-04-07

申请人： ETRON TECHNOLOGY, INC.

发明人： Chao-Chun Lu ,  Bor-Doou Rong ,  Chun Shiah

IPC分类号： G11C11/406 ,  G11C11/4091

CPC分类号： G11C11/40626 ,  G11C11/4091

摘要： The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

公开(公告)号：US20230317693A1

公开(公告)日：2023-10-05

申请号：US17954837

申请日：2022-09-28

申请人： nD-HI Technologies Lab, Inc. ,  ETRON TECHNOLOGY, INC.

发明人： Ho-Ming TONG ,  Chao-Chun LU

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L25/16 ,  H01L24/24 ,  H01L24/16 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L24/96 ,  H01L21/566 ,  H01L21/561 ,  H01L23/3128 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19104 ,  H01L2224/24101 ,  H01L2224/24195 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48229 ,  H01L2224/4814 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/73207 ,  H01L2224/95001 ,  H01L21/563

摘要： A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.

公开(公告)号：US20230207645A1

公开(公告)日：2023-06-29

申请号：US18111899

申请日：2023-02-21

申请人： Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

发明人： Chao-Chun Lu ,  Li-Ping Huang

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/41791 ,  H01L29/785 ,  H01L29/1083 ,  H01L29/7833 ,  H01L29/7835

摘要： A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

公开(公告)号：US20220156223A1

公开(公告)日：2022-05-19

申请号：US17391755

申请日：2021-08-02

申请人： ETRON TECHNOLOGY, INC.

发明人： Chun SHIAH

IPC分类号： G06F13/42 ,  G06F13/16

摘要： A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

公开(公告)号：US20210408245A1

公开(公告)日：2021-12-30

申请号：US17151635

申请日：2021-01-18

申请人： Etron Technology, Inc.

发明人： Chao-Chun Lu

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66

摘要： A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

公开(公告)号：US20210351272A1

公开(公告)日：2021-11-11

申请号：US16991044

申请日：2020-08-12

申请人： Etron Technology, Inc.

发明人： Chao-Chun Lu

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

摘要： A transistor structure includes a semiconductor substrate, agate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a first metal containing region under the semiconductor surface.

公开(公告)号：US20210295893A1

公开(公告)日：2021-09-23

申请号：US17333836

申请日：2021-05-28

申请人： ETRON TECHNOLOGY, INC.

发明人： Chao-Chun LU ,  Bor-Doou RONG ,  Chun SHIAH

IPC分类号： G11C11/4074 ,  G11C11/4096

摘要： This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

公开(公告)号：US11056174B2

公开(公告)日：2021-07-06

申请号：US16702509

申请日：2019-12-03

申请人： Etron Technology, Inc.

发明人： Chao-Chun Lu

IPC分类号： G11C7/22 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/419

摘要： A DRAM chip includes a DRAM cell and a first voltage source. The DRAM cell includes an access transistor, and one terminal of the access transistor is coupled to a word line. The first voltage source is selectively coupled to the access transistor via the word line, and generates a first voltage level higher than a sum of a threshold voltage of the access transistor and a voltage level of a signal ONE utilized in the DRAM chip. A whole access cycle includes an access operation period and a restore phase period. When the whole access cycle begins, the one terminal of the access transistor is initially applied by the first voltage level for a first portion of the access operation period and then applied by a second voltage level for a second portion of the access operation period. The second voltage level is lower than the first voltage level.

公开(公告)号：US20210183415A1

公开(公告)日：2021-06-17

申请号：US17100955

申请日：2020-11-23

申请人： Etron Technology, Inc.

发明人： Chun Shiah

IPC分类号： G11C7/10 ,  G11C7/22

摘要： A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.