- 专利标题： MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE/DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD
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申请号： US17151635申请日： 2021-01-18
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公开(公告)号： US20210408245A1公开(公告)日： 2021-12-30
- 发明人: Chao-Chun Lu
- 申请人： Etron Technology, Inc.
- 申请人地址： TW Hsinchu
- 专利权人： Etron Technology, Inc.
- 当前专利权人： Etron Technology, Inc.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L29/417
- IPC分类号： H01L29/417 ; H01L29/06 ; H01L29/78 ; H01L21/762 ; H01L29/40 ; H01L29/66
摘要：
A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.
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