知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

159 records (took 0.037 seconds)

    Techniques for MRAM MTJ top electrode connection
    141.
    发明授权
    Techniques for MRAM MTJ top electrode connection 有权

    公开(公告)号：US10535814B2

    公开(公告)日：2020-01-14

    申请号：US15809182

    申请日：2017-11-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

    IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12

    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

    Structure and formation method of integrated circuit structure
    142.
    发明授权
    Structure and formation method of integrated circuit structure 有权

    公开(公告)号：US10134807B2

    公开(公告)日：2018-11-20

    申请号：US15460902

    申请日：2017-03-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Hung-Cho Wang ,  Wen-Chun You

    IPC: H01L29/82 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

    Abstract: Integrated circuit structures and methods for forming the same are provided. An integrated circuit includes a dielectric layer in a memory region and a logic region. The integrated circuit structure also includes a first conductive feature in the dielectric layer in the memory region. The integrated circuit structure further includes a second conductive feature in the dielectric layer in the logic region. In addition, the integrated circuit structure includes an active memory cell over the dielectric layer in the memory region. The active memory cell is connected to the first conductive feature. The integrated circuit structure also includes a dummy memory cell over the dielectric layer in the logic region. The dummy memory cell is connected to the second conductive feature.

    Embedded memory device between noncontigous interconnect metal layers
    146.
    发明授权
    Embedded memory device between noncontigous interconnect metal layers 有权

    公开(公告)号：US09893278B1

    公开(公告)日：2018-02-13

    申请号：US15230690

    申请日：2016-08-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chun-Heng Liao

    IPC: H01L47/00 ,  H01L45/00 ,  H01L27/22

    CPC classification number: H01L45/1233 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/146

    Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a memory region and a logic region. A lower metal layer is disposed over a substrate, and comprises a first lower metal line within the memory region. An upper metal layer overlies the lower metal layer, and comprises a first upper metal line within the memory region. A memory cell is disposed between the first lower metal line and the first upper metal line, and comprises a planar bottom electrode. The planar bottom electrode abuts a first lower metal via of the lower metal layer. By forming the planar bottom electrode and connecting the planar bottom electrode to the lower metal layer through the lower metal via, no additional BEVA planarization and/or patterning processes are needed. As a result, risk of damaging the lower metal lines are reduced, thereby providing more reliable read/write operations and/or better performance.

    METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
    150.
    发明申请
    METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE 有权
    用低功率逻辑器件形成分离式闪存存储器单元设备的方法

    公开(公告)号：US20160365350A1

    公开(公告)日：2016-12-15

    申请号：US15245539

    申请日：2016-08-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/3213

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

    Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

    Abstract translation: 提供了一种制造嵌入式闪存设备的方法。 一对栅极叠层形成在半导体衬底上间隔开，并且在浮动栅极上包括浮动栅极和控制栅极。 在栅极堆叠和半导体衬底上形成公共栅极层，并且栅极堆叠的衬里侧壁。 在公共栅极层中执行第一蚀刻，以将公共栅极层的上表面分别凹入栅极堆叠的下表面，并在栅极堆叠之间形成擦除栅极。 硬掩模分别形成在擦除栅极，公共栅极层的字线区域和公共栅极层的逻辑门极区域上。 第二蚀刻被执行到具有硬掩模的公共栅层中，以同时形成字线和逻辑门。

Patent Agency Ranking