公开(公告)号：US11935754B2

公开(公告)日：2024-03-19

申请号：US17854175

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/28568 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

公开(公告)号：US11923414B2

公开(公告)日：2024-03-05

申请号：US17841217

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02631

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

公开(公告)号：US20240021697A1

公开(公告)日：2024-01-18

申请号：US18366073

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L21/28556 ,  H01L29/66545 ,  H01L29/401

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US20240021680A1

公开(公告)日：2024-01-18

申请号：US18446681

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/66742 ,  H01L21/28035 ,  H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823462 ,  H01L21/28088 ,  H01L29/78645

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US11824100B2

公开(公告)日：2023-11-21

申请号：US17232282

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/16 ,  H01L29/20 ,  H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L21/28556 ,  H01L29/401 ,  H01L29/66545

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US11810961B2

公开(公告)日：2023-11-07

申请号：US17220076

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.

公开(公告)号：US20230343822A1

公开(公告)日：2023-10-26

申请号：US17867804

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

公开(公告)号：US20230282725A1

公开(公告)日：2023-09-07

申请号：US18316419

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4908 ,  H01L29/66742 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L27/092

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

公开(公告)号：US11715762B2

公开(公告)日：2023-08-01

申请号：US17220335

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L29/0673 ,  H01L21/2654 ,  H01L27/0924

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US11637180B2

公开(公告)日：2023-04-25

申请号：US17224555

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.