公开(公告)号：US20230170218A1

公开(公告)日：2023-06-01

申请号：US18161662

申请日：2023-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266

CPC classification number: H01L21/0337 ,  C23C16/042 ,  C23C16/50 ,  C23C16/4582 ,  H01L21/266 ,  H01L21/02274 ,  H01L21/3086 ,  H01L21/32051

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

公开(公告)号：US11664268B2

公开(公告)日：2023-05-30

申请号：US17373339

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US11495460B2

公开(公告)日：2022-11-08

申请号：US16986374

申请日：2020-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate, and forming a first layer over the material layer. The method also includes forming a second layer over the first layer, and the second layer includes an auxiliary. The method further includes forming a third layer over the second layer, and the third layer includes an inorganic material, the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. A topmost surface of the second layer is in direct contact with a bottommost surface of the third layer. The method includes exposing a portion of the second layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process.

公开(公告)号：US11429027B2

公开(公告)日：2022-08-30

申请号：US16534965

申请日：2019-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng Yu ,  Ru-Gun Liu ,  Hsu-Ting Huang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F1/26 ,  G03F1/22 ,  G03F1/30

Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

公开(公告)号：US11378884B2

公开(公告)日：2022-07-05

申请号：US16725884

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Ya-Ching Chang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/38 ,  G03F7/30 ,  G03F7/039 ,  G03F7/32 ,  G03F7/20

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate. The photoresist layer includes at least an acid labile group (ALG) and a thermo-base generator (TBG). The method further includes exposing a portion of the photoresist layer to a radiation and performing a baking process after the exposing of the portion of the photoresist layer. The TBG releases a base during the performing of the baking process, resulting in a chemical reaction between the ALG and the base. The method further includes removing an unexposed portion of the photoresist layer, resulting in a patterned photoresist layer.

公开(公告)号：US11307504B2

公开(公告)日：2022-04-19

申请号：US16905167

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Joy Cheng

IPC: G03F7/20 ,  G03F7/038 ,  G03F7/039 ,  G03F7/06 ,  G03F7/16 ,  G03F7/30 ,  G03F7/32 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027

Abstract: A layer is formed over a wafer. The layer contains a material that is sensitive to an extreme ultraviolet (EUV) radiation. A first baking process is performed to the layer. The first baking process is performed with a first humidity level that is greater than about 44%. After the first baking process, the layer is exposed to EUV radiation. A second baking process is performed to the layer. The second baking process is performed with a second humidity level that is greater than about 44%. The layer is rinsed with a liquid that contains water before the second baking process or after the second baking process. After the exposing, the layer is developed with a developer solution that contains water.

公开(公告)号：US11289332B2

公开(公告)日：2022-03-29

申请号：US16512336

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chin-Hsiang Lin ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

公开(公告)号：US11262659B2

公开(公告)日：2022-03-01

申请号：US16547317

申请日：2019-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang

IPC: G03F7/20 ,  G03B27/42

Abstract: A method of cleaning an extreme ultraviolet lithography collector includes applying a cleaning composition to a surface of the extreme ultraviolet lithography collector having debris on the surface of the collector in an extreme ultraviolet radiation source chamber. The cleaning composition includes: a major solvent having Hansen solubility parameters of 25>δd>15, 25>δp>10, and 30>δh>6; and an acid having an acid dissociation constant, pKa, of −15

公开(公告)号：US20210358752A1

公开(公告)日：2021-11-18

申请号：US17384921

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

公开(公告)号：US11150561B2

公开(公告)日：2021-10-19

申请号：US16927131

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen Cho ,  Fu-Jye Liang ,  Chun-Kuang Chen ,  Chih-Tsung Shih ,  Li-Jui Chen ,  Po-Chung Cheng ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/22 ,  G03F1/22 ,  G03F1/44 ,  G03F1/36 ,  G06T7/00

Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.