公开(公告)号：US5023478A

公开(公告)日：1991-06-11

申请号：US493079

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

CPC分类号： H03K19/013 ,  H03F1/308 ,  H03F3/3008 ,  H03F3/3071 ,  H03K17/667

摘要： The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.

公开(公告)号：US4729006A

公开(公告)日：1988-03-01

申请号：US840180

申请日：1986-03-17

申请人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L21/76224

摘要： A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

摘要翻译： 一种用于在用于制造CMOS集成电路的半导体上形成完全凹陷（平面）隔离区域的方法，所得到的半导体结构包括在其中形成有台面的P掺杂硅衬底中，形成接触的硼硅酸盐玻璃的低粘度侧壁间隔物 其中所述台面的侧壁被指定为在其中形成有N沟道器件; 然后用TEOS填充与台面相邻的基板中的沟槽; 并加热该结构直到侧壁间隔物中的硼扩散到指定台面的侧壁中以形成通道停止点。 这些侧壁间隔件通过减轻TEOS中的内部机械应力来减少TEOS中的裂纹的发生，并允许通过扩散形成通道停止，从而允许台面壁基本上垂直。

公开(公告)号：US4671851A

公开(公告)日：1987-06-09

申请号：US791861

申请日：1985-10-28

申请人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/31053 ,  H01L21/743 ,  H01L21/76202

摘要： A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

摘要翻译： 用于去除硅片表面的SiO 2突起的化学机械（化学机械）方法，包括“鸟头”的突起。 将Si 3 N 4的薄的蚀刻停止层沉积在晶片表面上，然后用SiO 2水基浆料进行化学研磨。 Si 3 N 4仅在晶片表面的平面部分上用作抛光或蚀刻阻挡层。 位于“鸟头”顶部和侧壁处的Si 3 N 4层的部分和下面的SiO 2突起被去除以提供基本平坦的整体结构。

公开(公告)号：US07411247B2

公开(公告)日：2008-08-12

申请号：US11652888

申请日：2007-01-12

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US07394703B2

公开(公告)日：2008-07-01

申请号：US11409382

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US07382659B2

公开(公告)日：2008-06-03

申请号：US11409372

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US20060187709A1

公开(公告)日：2006-08-24

申请号：US11409376

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/115 ,  H01L29/7923

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

摘要翻译： 本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。 控制栅极和字栅之间的垂直绝缘体不包括氮化物层。 这样可以防止电子捕获的问题。 可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。 该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。 双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

公开(公告)号：US20050164451A1

公开(公告)日：2005-07-28

申请号：US11059080

申请日：2005-02-16

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/02 ,  H01L29/423 ,  H01L29/792 ,  H01L47/00

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US06545312B2

公开(公告)日：2003-04-08

申请号：US09897417

申请日：2001-07-03

申请人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

发明人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

公开(公告)号：US06531350B2

公开(公告)日：2003-03-11

申请号：US09994084

申请日：2001-11-21

申请人： Kimihiro Satoh ,  Seiki Ogura ,  Tomoya Saito

发明人： Kimihiro Satoh ,  Seiki Ogura ,  Tomoya Saito

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S257/906 ,  Y10S438/954

摘要： Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.

摘要翻译： 在本发明中提出了一种用于集成双MONOS存储单元阵列和CMOS逻辑器件电路的高密度双MONOS存储器件的制造方法及其阵列组织。 本发明由两种制造方法组成：i）同时定义存储器栅极和逻辑门，从而改进工艺集成方案，以便更容易和更可靠的制造.ii）位线跨越字门和控制栅极。 本发明着重于降低寄生薄片电阻以实现高速同时保持低的制造成本。 双MONOS单元将存储器存储在选择栅极的两个侧壁上的两个共享控制栅极下的两个氮化物存储单元元件中。 该方法适用于具有平坦通道的设备和/或具有步进通道的设备。本发明的两个实施例被公开。