公开(公告)号：US08490029B2

公开(公告)日：2013-07-16

申请号：US13421400

申请日：2012-03-15

申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

公开(公告)号：US08236709B2

公开(公告)日：2012-08-07

申请号：US12511535

申请日：2009-07-29

申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

IPC分类号： H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

公开(公告)号：US20120083092A1

公开(公告)日：2012-04-05

申请号：US13323033

申请日：2011-12-12

申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/02

CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

公开(公告)号：US07687338B2

公开(公告)日：2010-03-30

申请号：US11950572

申请日：2007-12-05

申请人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

发明人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S257/90

摘要： Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

摘要翻译： 本发明的实施例提供了通过一次性间隔物工艺在p型场效应晶体管（pFET）的源区和漏区中形成嵌入硅锗（eSiGe）的方法; 在第一过程中在源极和漏极区域中的eSiGe上直接沉积间隙填充层; 在与第一工艺不同的第二工艺中，在间隙填充层的顶部上沉积一层偏移间隔物材料; 蚀刻偏移间隔物材料和间隙填充层，从而形成一组偏移间隔物并暴露p​​FET的源区和漏区中的eSiGe; 并完成pFET的形成。

公开(公告)号：US5132765A

公开(公告)日：1992-07-21

申请号：US648797

申请日：1991-01-31

申请人： Jeffrey L. Blouse ,  Inge G. Fulton ,  Russell C. Lange ,  Bernard S. Meyerson ,  Karen A. Nummy ,  Martin Revitz ,  Robert Rosenberg

发明人： Jeffrey L. Blouse ,  Inge G. Fulton ,  Russell C. Lange ,  Bernard S. Meyerson ,  Karen A. Nummy ,  Martin Revitz ,  Robert Rosenberg

IPC分类号： H01L21/285 ,  H01L21/331

CPC分类号： H01L29/66287 ,  H01L21/28525

摘要： There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.

摘要翻译： 提供了一种用于制造晶体管的方法，所述方法包括以下步骤：提供包括第一导电类型区域的半导体材料的衬底; 在所述区域上形成第二导电类型外延半导体材料的第一层; 在所述第一层上形成第二导电类型外延半导体材料的第二层，所述第二层具有比所述第一层相对较高的掺杂剂浓度; 氧化第二层的一部分; 以及去除所述第二层的氧化部分以暴露所述第一层的一部分，所述第一层的暴露部分形成本征基区。 形成第一层和第二层的步骤优选使用低温，超高真空，外延沉积工艺进行。

公开(公告)号：US08507915B2

公开(公告)日：2013-08-13

申请号：US13307787

申请日：2011-11-30

申请人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

发明人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

IPC分类号： H01L29/94

CPC分类号： H01L21/4846 ,  H01L21/82 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/66636 ,  H01L29/945

摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

公开(公告)号：US08343825B2

公开(公告)日：2013-01-01

申请号：US13009020

申请日：2011-01-19

申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

公开(公告)号：US20090146223A1

公开(公告)日：2009-06-11

申请号：US11950574

申请日：2007-12-05

申请人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

发明人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

IPC分类号： H01L29/94 ,  H01L21/8236

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/808 ,  H01L29/812

摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.

摘要翻译： 一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加 更多的杂质）。 然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。 之后，在栅极导体的侧壁上形成永久的间隔物。 然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。 这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

公开(公告)号：US4671851A

公开(公告)日：1987-06-09

申请号：US791861

申请日：1985-10-28

申请人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/31053 ,  H01L21/743 ,  H01L21/76202

摘要： A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

摘要翻译： 用于去除硅片表面的SiO 2突起的化学机械（化学机械）方法，包括“鸟头”的突起。 将Si 3 N 4的薄的蚀刻停止层沉积在晶片表面上，然后用SiO 2水基浆料进行化学研磨。 Si 3 N 4仅在晶片表面的平面部分上用作抛光或蚀刻阻挡层。 位于“鸟头”顶部和侧壁处的Si 3 N 4层的部分和下面的SiO 2突起被去除以提供基本平坦的整体结构。

公开(公告)号：US09059320B2

公开(公告)日：2015-06-16

申请号：US13408187

申请日：2012-02-29

申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

摘要翻译： 提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。 电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。 保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。