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111.发明申请公开(公告)号：US20180331691A1
公开(公告)日：2018-11-15
申请号：US15977987
申请日：2018-05-11
IPC分类号： H03M1/66
摘要： A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.
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公开(公告)号：US20180302048A1
公开(公告)日：2018-10-18
申请号：US15520378
申请日：2015-10-20
CPC分类号： H03F3/2175 , H03F3/19 , H03F2200/171 , H03F2200/331 , H03F2200/451 , H03M3/30 , H03M3/422 , H03M3/466 , H03M3/47 , H03M3/50 , H04B1/04 , H04B1/16 , H04B2001/0408
摘要： A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.
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公开(公告)号：US09912144B2
公开(公告)日：2018-03-06
申请号：US14477236
申请日：2014-09-04
摘要： Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.
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公开(公告)号：US09859914B1
公开(公告)日：2018-01-02
申请号：US15647253
申请日：2017-07-11
申请人： MEDIATEK INC.
发明人： Chan-Hsiang Weng , Tien-Yu Lo
摘要： A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.
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公开(公告)号：US09825645B1
公开(公告)日：2017-11-21
申请号：US15389297
申请日：2016-12-22
CPC分类号： H03M3/422 , H03M1/00 , H03M1/0624 , H03M1/12 , H03M1/52 , H03M3/30 , H03M3/454 , H03M3/46 , H03M2201/4233
摘要： The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.
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公开(公告)号：US09748970B1
公开(公告)日：2017-08-29
申请号：US15365947
申请日：2016-12-01
申请人： NXP USA, INC.
发明人： Zhou Fang , Song Huang , Chao Liang , Yifeng Liu , Wanggen Zhang
摘要： A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.
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公开(公告)号：US20170201270A1
公开(公告)日：2017-07-13
申请号：US15276561
申请日：2016-09-26
IPC分类号： H03M3/00
摘要： A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.
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公开(公告)号：US09692445B1
公开(公告)日：2017-06-27
申请号：US15072837
申请日：2016-03-17
CPC分类号： H03M3/30 , G06G7/26 , H03M3/50 , H03M7/3042
摘要： A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.
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公开(公告)号：US20170179976A1
公开(公告)日：2017-06-22
申请号：US15369777
申请日：2016-12-05
申请人： IMEC VZW
IPC分类号： H03M3/00
摘要： A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.
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公开(公告)号：US09575729B1
公开(公告)日：2017-02-21
申请号：US14999288
申请日：2016-04-21
申请人： Djuro G. Zrilic
发明人： Djuro G. Zrilic
CPC分类号： G06F7/602 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/444 , H03M3/458 , H03M3/476 , H04L27/2647
摘要： Disclosed is a completely digital solution for a new type of root-mean-square to direct current conversion (RMS-to-DC) apparatus. The design is based on delta-sigma modulation (Δ-ΣM) and the direct nonlinear processing of the Δ-Σ modulated pulse stream. The only external component of the integrated circuit (IC) is capacitor C. The disclosed apparatus consists of low power consuming components which are simple, reliable and inexpensive.
摘要翻译： 公开了一种用于新型均方根直流电转换（RMS-to-DC）装置的完全数字解决方案。 该设计基于Δ-Σ调制（Δ-ΣM）和Δ-Σ调制脉冲流的直接非线性处理。 集成电路（IC）的唯一的外部部件是电容器C.所公开的装置由简单，可靠和便宜的低功耗部件组成。
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