公开(公告)号：US20180059178A1

公开(公告)日：2018-03-01

申请号：US15365890

申请日：2016-11-30

Applicant: NXP USA, INC.

Inventor： Ling Wang ,  Wanggen Zhang ,  Wei Zhang

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/318541 ,  G01R31/318575

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.

公开(公告)号：US09748970B1

公开(公告)日：2017-08-29

申请号：US15365947

申请日：2016-12-01

Applicant: NXP USA, INC.

Inventor： Zhou Fang ,  Song Huang ,  Chao Liang ,  Yifeng Liu ,  Wanggen Zhang

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/66

CPC classification number: H03M3/50 ,  H03M1/1071 ,  H03M1/108 ,  H03M1/66 ,  H03M3/30 ,  H03M3/378 ,  H03M3/458

Abstract: A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.

公开(公告)号：US10338136B2

公开(公告)日：2019-07-02

申请号：US15365890

申请日：2016-11-30

Applicant: NXP USA, INC.

Inventor： Ling Wang ,  Wanggen Zhang ,  Wei Zhang

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/34

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.