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公开(公告)号：US20070085717A1
公开(公告)日：2007-04-19
申请号：US10573053
申请日：2004-09-22
Applicant: Kim Pedersen , Lars Arkanaes-Pedersen
Inventor： Kim Pedersen , Lars Arkanaes-Pedersen
IPC: H03M3/00
Abstract: The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.
Abstract translation: 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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公开(公告)号：US20170288692A1
公开(公告)日：2017-10-05
申请号：US15494408
申请日：2017-04-21
Applicant: INTEL IP CORPORATION
Inventor： John G. KAUFFMAN , Krzysztof DUFRENE
CPC classification number: H03M3/356 , H03M1/00 , H03M1/0607 , H03M1/12 , H03M1/46 , H03M3/30 , H03M3/386 , H03M3/424 , H03M3/444 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.
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公开(公告)号：US08842031B1
公开(公告)日：2014-09-23
申请号：US13932830
申请日：2013-07-01
Applicant: Cirrus Logic, Inc.
Inventor： Mohammad Ranjbar , Bruce Eliot Duewer
IPC: H03M3/00
CPC classification number: H03M3/444
Abstract: The stability of a delta-sigma modulator may be improved by limiting a value within the delta-sigma modulator. For example, the value provided to a quantizer may be limited, by a limiter circuit in the delta-sigma modulator, to a value within a single step range of the quantizer. The limiter circuit may be placed in an inner loop of the delta-sigma modulator to decouple the stability of the inner loop from an outer loop. For example, a delta-sigma modulator may be constructed with an inner loop having a sixth order and an outer loop having a second order, in which the stability of the delta-sigma modulator is proportional to that of a second order.
Abstract translation: 通过限制δ-Σ调制器内的值，可以提高Δ-Σ调制器的稳定性。 例如，提供给量化器的值可以通过Δ-Σ调制器中的限幅器电路限制在量化器的单个步长范围内的值。 限制器电路可以放置在Δ-Σ调制器的内环中，以将内环的稳定性与外环隔离。 例如，Δ-Σ调制器可以被构造成具有具有第六级的内环和具有二阶的外环，其中Δ-Σ调制器的稳定性与第二级的稳定性成比例。
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公开(公告)号：US07388530B2
公开(公告)日：2008-06-17
申请号：US10573053
申请日：2004-09-22
Applicant: Kim Rishøj Pedersen , Lars Arknæs-Pedersen
Inventor： Kim Rishøj Pedersen , Lars Arknæs-Pedersen
IPC: H03M3/00
Abstract: The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.
Abstract translation: 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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公开(公告)号：US09680496B2
公开(公告)日：2017-06-13
申请号：US14751063
申请日：2015-06-25
Applicant: Intel IP Corporation
Inventor： John G. Kauffman , Krzysztof Dufrene
CPC classification number: H03M3/356 , H03M1/00 , H03M1/0607 , H03M1/12 , H03M1/46 , H03M3/386 , H03M3/424 , H03M3/444 , H03M3/454 , H03M3/464
Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.
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Patent Agency Ranking
公开(公告)号：US20140167995A1
公开(公告)日：2014-06-19
申请号：US14111016
申请日：2012-04-11
Applicant: Kei Tee Tiew , Kok Lim Chan , Minkyu Je , Xiaojun Yuan
Inventor： Kei Tee Tiew , Kok Lim Chan , Minkyu Je , Xiaojun Yuan
Abstract: According to embodiments of the present invention, an analog-to-digital converter is provided. The analog-to-digital converter includes an input configured to receive an input signal, a feed-forward path connected to the input configured to feed forward the input signal, a processing path including a loop filter, wherein the loop filter includes at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter, a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path, a quantizer configured to generate an output signal of the converter, a feed-back path configured to feed back the output signal, and a second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path.
Abstract translation: 根据本发明的实施例，提供了一种模拟 - 数字转换器。 模数转换器包括被配置为接收输入信号的输入端，连接到被配置为向前馈送输入信号的输入端的前馈路径，包括环路滤波器的处理路径，其中环路滤波器包括至少一个 局部反馈路径，被配置为将环路滤波器的输出信号反馈到环路滤波器的输入;第一组合器，被配置为将由前馈路径馈送的输入信号与处理路径的输出组合;量化器配置 以产生转换器的输出信号，被配置为反馈输出信号的反馈路径和第二组合器，其中处理路径连接到第二组合器，并且第二组合器被配置为将输入信号与馈送 转换器的反向输出信号，并将组合的结果提供给处理路径。
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公开(公告)号：US07379001B2
公开(公告)日：2008-05-27
申请号：US10573059
申请日：2003-09-22
Applicant: Kim Rishøj Pedersen , Lars Arknæs-Pedersen
Inventor： Kim Rishøj Pedersen , Lars Arknæs-Pedersen
IPC: H03M3/00
Abstract: The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.
Abstract translation: 本发明涉及包括至少一个正向路径（FP），至少一个反馈路径（FBP）的至少一个自振荡回路（SOL），其中所述至少一个前向路径（FP）包括组合的幅度量化装置（AQM） 具有时间量化装置（TQM）并且输出至少一个时间和幅度量化信号（OS）。 根据本发明，可以获得高速高分辨率A / D转换器。
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公开(公告)号：US07123177B2
公开(公告)日：2006-10-17
申请号：US10640633
申请日：2003-08-14
Applicant: Taiyi Cheng , Josephus van Engelen , Minsheng Wang
Inventor： Taiyi Cheng , Josephus van Engelen , Minsheng Wang
IPC: H03M3/00
Abstract: A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.
Abstract translation: 提供了一种用于稳定高阶Σ-Δ调制器的系统和方法。 该系统包括在积分器的反馈路径中具有限幅器的积分器。 积分器将输入信号与限幅器产生的反馈信号相结合，产生一个集成的输出信号。 输出信号输出到Σ-Δ调制器的下一个分量。 此外，输出信号通过限幅器反馈。 当限制器在反馈路径中接收的输出信号超过限幅器的阈值时，限幅器被激活并钳位输出信号以产生有限的信号。 有限信号与输入信号组合到积分器以产生输出信号。
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9.发明授权CMOS differential amplifier for a delta sigma modulator applicable for an analog-to-digital converter 失效适用于模数转换器的三角形Σ调制器的CMOS差分放大器
公开(公告)号：US6018262A
公开(公告)日：2000-01-25
申请号：US67046
申请日：1998-04-27
Applicant: Masao Noro , Yusuke Yamamoto , Toshio Maejima
Inventor： Masao Noro , Yusuke Yamamoto , Toshio Maejima
Abstract: An analog-digital converter includes a .DELTA..SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA..SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA..SIGMA. modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.
Abstract translation: 模拟数字转换器包括串联连接的DELTA SIGMA调制器，数字滤波器，高通滤波器和乘法器。 模拟输入通过DELTA SIGMA调制器转换成串行位串，为其设置增益'1 / A'。 数字滤波器从串行比特串中提取与模拟输入相对应的低频分量，因此低频分量转换为并行位数字数据。 高通滤波器从数字滤波器的输出中去除直流偏移分量; 然后，通过乘法器将其输出乘以缩放增益“A”，从而产生数字输出。 DELTA SIGMA调制器包括串联连接的至少三个开关电容积分器和一位量化器以及单采样延迟电路。 由一位量化器产生的一位输出由单采样延迟电路延迟，其中输出被传送到每个开关电容积分器。 每个开关电容积分器使用由CMOS运算放大器和至少一个幅度限制电路配置的CMOS差分放大器来配置。 限幅电路由两个PMOS晶体管和两个以二极管连接方式并联连接的NMOS晶体管构成; 并且该电路被提供以通过稳定其工作点来限制CMOS差分放大器的输出的幅度。
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公开(公告)号：US09575729B1
公开(公告)日：2017-02-21
申请号：US14999288
申请日：2016-04-21
Applicant: Djuro G. Zrilic
Inventor： Djuro G. Zrilic
CPC classification number: G06F7/602 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/444 , H03M3/458 , H03M3/476 , H04L27/2647
Abstract: Disclosed is a completely digital solution for a new type of root-mean-square to direct current conversion (RMS-to-DC) apparatus. The design is based on delta-sigma modulation (Δ-ΣM) and the direct nonlinear processing of the Δ-Σ modulated pulse stream. The only external component of the integrated circuit (IC) is capacitor C. The disclosed apparatus consists of low power consuming components which are simple, reliable and inexpensive.
Abstract translation: 公开了一种用于新型均方根直流电转换（RMS-to-DC）装置的完全数字解决方案。 该设计基于Δ-Σ调制（Δ-ΣM）和Δ-Σ调制脉冲流的直接非线性处理。 集成电路（IC）的唯一的外部部件是电容器C.所公开的装置由简单，可靠和便宜的低功耗部件组成。
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