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公开(公告)号：US20180343013A1
公开(公告)日：2018-11-29
申请号：US15926442
申请日：2018-03-20
Applicant: NXP B.V.
Inventor： Lucien Johannes BREEMS , Muhammed BOLATKALE , Chenming ZHANG
IPC: H03M3/00
Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.
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公开(公告)号：US20180048326A1
公开(公告)日：2018-02-15
申请号：US15652252
申请日：2017-07-18
Applicant: MEDIATEK INC.
Inventor： Pao-Cheng Chiu , Hung-Yi Hsieh
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.
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公开(公告)号：US09838031B2
公开(公告)日：2017-12-05
申请号：US15360984
申请日：2016-11-23
Applicant: Analog Devices Global
Inventor： Yunzhi Dong , Hajime Shibata , Trevor Clifford Caldwell , Zhao Li , Jialin Zhao , Jose Barreiro Silva
CPC classification number: H03M3/422 , H03M1/361 , H03M3/322 , H03M3/344 , H03M3/378 , H03M3/388 , H03M3/414 , H03M3/436 , H03M3/464
Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.
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公开(公告)号：US09793908B2
公开(公告)日：2017-10-17
申请号：US15360816
申请日：2016-11-23
Applicant: Analog Devices Global
Inventor： Hajime Shibata
IPC: H03M1/06 , H02H9/04 , H03M1/12 , H03K17/082 , H03M3/00
CPC classification number: H03M1/06 , H02H9/04 , H03K17/0822 , H03M1/129 , H03M3/322 , H03M3/414 , H03M3/458
Abstract: Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage
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公开(公告)号：US20170179975A1
公开(公告)日：2017-06-22
申请号：US15360984
申请日：2016-11-23
Applicant: Analog Devices Global
Inventor： YUNZHI DONG , Hajime SHIBATA , Trevor Clifford CALDWELL , Zhao LI , Jialin ZHAO , Jose Barreiro SILVA
IPC: H03M3/00
CPC classification number: H03M3/422 , H03M1/361 , H03M3/322 , H03M3/344 , H03M3/378 , H03M3/388 , H03M3/414 , H03M3/436 , H03M3/464
Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.
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Patent Agency Ranking
6.发明授权Method and apparatus for separating the reference current from the input signal in sigma-delta converter 有权用于在Σ-Δ转换器中分离参考电流与输入信号的方法和装置公开(公告)号：US09124290B2
公开(公告)日：2015-09-01
申请号：US13757455
申请日：2013-02-01
Applicant: Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
Inventor： Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.
Abstract translation: 积分器系统可以具有一对采样电路，每个采样电路各自具有采样电容器以对差分输入信号的相应分量进行采样，以及具有耦合到采样电路的输出的输入的积分器。 该系统可以具有耦合在采样电容器的输入端之间的短路开关。 在采样电路的采样和输出阶段之间的间隙阶段，短路开关可能被接合。 通过将采样电容器的输入端子短路在一起，该设计减少了系统吸收的电流，并且在一些设计中，切断了电流抽取与系统采样的信息内容之间的关系。 积分器系统可以接收模拟和数字输入信号。
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公开(公告)号：US09059732B2
公开(公告)日：2015-06-16
申请号：US13848208
申请日：2013-03-21
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher J. Courtney
CPC classification number: H03M1/645 , G01D5/2073 , G01P3/489 , H03M1/0617 , H03M1/485 , H03M3/322
Abstract: According to one aspect, a resolver-to-digital converter includes a first filter configured to receive a first delta-sigma modulated resolver input. A second filter is configured to receive a second delta-sigma modulated resolver input. A summing junction is configured to output a difference between a scaled output of the first filter and a scaled output of the second filter. A controller is configured to generate a controller output based on a product of a demodulator and an output of the summing junction. An integrator is configured to generate an estimated position based on the controller output. The resolver-to-digital converter also includes a compensator configured to generate a compensated estimated position based on the controller output and a compensation offset delay adjustment.
Abstract translation: 根据一个方面，解算器到数字转换器包括被配置为接收第一delta-sigma调制解调器输入的第一滤波器。 第二滤波器被配置为接收第二Δ-Σ调制分解器输入。 求和点被配置为输出第一滤波器的缩放输出和第二滤波器的缩放输出之间的差。 控制器被配置为基于解调器的乘积和求和结点的输出来产生控制器输出。 积分器被配置为基于控制器输出生成估计位置。 解算器到数字转换器还包括被配置为基于控制器输出和补偿偏移延迟调整产生补偿估计位置的补偿器。
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公开(公告)号：US09024795B2
公开(公告)日：2015-05-05
申请号：US14260899
申请日：2014-04-24
Applicant: Micronas GmbH
Inventor： David Muthers
IPC: H03M3/00
Abstract: A continuous-time delta sigma modulator, having an integrator and a comparator clocked with a clock frequency that are connected in a feedback loop, having a voltage source that is connected to the comparator for applying a threshold voltage to the comparator, in which an integration time constant of the integrator has a first resistor and a first capacitor, in which the voltage source has a second resistor and a second capacitor for setting the threshold voltage, in which the first resistor and the second resistor are part of a resistor pairing structure, and in which the first capacitor and the second capacitor are part of a capacitor pairing structure.
Abstract translation: 具有积分器和时钟频率的比较器的连续时间ΔΣ调制器连接在反馈回路中，具有连接到比较器的电压源，用于向比较器施加阈值电压，其中积分 积分器的时间常数具有第一电阻器和第一电容器，其中电压源具有用于设置阈值电压的第二电阻器和第二电容器，其中第一电阻器和第二电阻器是电阻器配对结构的一部分， 并且其中第一电容器和第二电容器是电容器配对结构的一部分。
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公开(公告)号：US20150097709A1
公开(公告)日：2015-04-09
申请号：US13848208
申请日：2013-03-21
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher J. Courtney
CPC classification number: H03M1/645 , G01D5/2073 , G01P3/489 , H03M1/0617 , H03M1/485 , H03M3/322
Abstract: According to one aspect, a resolver-to-digital converter includes a first filter configured to receive a first delta-sigma modulated resolver input. A second filter is configured to receive a second delta-sigma modulated resolver input. A summing junction is configured to output a difference between a scaled output of the first filter and a scaled output of the second filter. A controller is configured to generate a controller output based on a product of a demodulator and an output of the summing junction. An integrator is configured to generate an estimated position based on the controller output. The resolver-to-digital converter also includes a compensator configured to generate a compensated estimated position based on the controller output and a compensation offset delay adjustment.
Abstract translation: 根据一个方面，解算器到数字转换器包括被配置为接收第一delta-sigma调制解调器输入的第一滤波器。 第二滤波器被配置为接收第二Δ-Σ调制分解器输入。 求和点被配置为输出第一滤波器的缩放输出和第二滤波器的缩放输出之间的差。 控制器被配置为基于解调器的乘积和求和结点的输出来产生控制器输出。 积分器被配置为基于控制器输出生成估计位置。 解算器到数字转换器还包括被配置为基于控制器输出和补偿偏移延迟调整产生补偿估计位置的补偿器。
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公开(公告)号：US08847805B1
公开(公告)日：2014-09-30
申请号：US13919747
申请日：2013-06-17
Applicant: Power Integrations, Inc.
Inventor： Frank J. Schulz
IPC: H03M3/00
Abstract: Measurement circuits having a delta-sigma modulator are disclosed. One example measurement circuit includes a low pass filter coupled to receive an input voltage, a switched-capacitor integrator circuit, and a switched comparator circuit. The measurement circuit may generate a digital output made up of a sequence of logic high and logic low levels that are representative of a scaled value of the input voltage output by the low pass filter circuit. Also, by virtue of its switched-capacitor configuration, the electric charge received by the switched difference amplifier circuit may be returned to the input in a manner such that the input to the delta-sigma modulator takes little to no average current from the voltage it measures. In other words, the delta-sigma modulator may have a high input impedance by virtue of its switched-capacitor circuit configuration.
Abstract translation: 公开了具有Δ-Σ调制器的测量电路。 一个示例性测量电路包括耦合以接收输入电压的低通滤波器，开关电容积分器电路和开关比较器电路。 测量电路可以产生由代表由低通滤波器电路输出的输入电压的定标值的逻辑高电平和逻辑低电平序列组成的数字输出。 此外，由于其开关电容器配置，由开关差分放大器电路接收的电荷可以以这样的方式返回到输入，使得对Δ-Σ调制器的输入几乎不需要与电压的平均电流 措施。 换句话说，Δ-Σ调制器可以通过其开关电容器电路配置具有高输入阻抗。
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