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公开(公告)号：US20170179969A1
公开(公告)日：2017-06-22
申请号：US15365867
申请日：2016-11-30
Applicant: ANALOG DEVICES GLOBAL
Inventor： Qingdong Meng , Hajime Shibata , Richard E. Schreier , Martin Steven McCormick , Yunzhi Dong , Jose Barreiro Silva , Jialin Zhao , Donald W. Paterson , Wenhua W. Yang
Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.
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公开(公告)号：US10181860B1
公开(公告)日：2019-01-15
申请号：US15794367
申请日：2017-10-26
Applicant: Analog Devices Global Unlimited Company
Inventor： Sharvil Pradeep Patil , Hajime Shibata , Wenhua William Yang , David Nelson Alldred , Yunzhi Dong , Gabriele Manganaro , Kimo Tam
Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.
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公开(公告)号：US10187075B1
公开(公告)日：2019-01-22
申请号：US15974548
申请日：2018-05-08
Applicant: Analog Devices Global Unlimited Company
Inventor： Sharvil Pradeep Patil , Hajime Shibata , Yunzhi Dong , David Nelson Alldred , Frank Murden , Lawrence A. Singer
Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are described. An exemplary system includes a filter, e.g. a FIR filter, for generating a filtered analog output based on an analog input, a quantizer for generating a digital input to a feedforward DAC based on the filtered analog output generated by the filter, a feedforward DAC for generating a feedforward path analog output based on the digital input generated by the quantizer, and a subtractor for generating a residue signal based on the feedforward path analog output. Providing a filter that filters the analog input before it is quantized advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer. At least some of the residue generation systems described herein may be implemented with relatively small design and power dissipation overheads.
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公开(公告)号：US09912342B2
公开(公告)日：2018-03-06
申请号：US15369175
申请日：2016-12-05
Applicant: Analog Devices Global
Inventor： Zhao Li , Hajime Shibata , Trevor Clifford Caldwell , Yunzhi Dong , Jialin Zhao , Richard E. Schreier , Victor Kozlov , David Nelson Alldred , Prawal Man Shrestha
CPC classification number: H03M1/1009 , H03M1/0626 , H03M1/066 , H03M1/1245 , H03M1/34 , H03M3/388 , H03M3/422
Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.
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公开(公告)号：US09838031B2
公开(公告)日：2017-12-05
申请号：US15360984
申请日：2016-11-23
Applicant: Analog Devices Global
Inventor： Yunzhi Dong , Hajime Shibata , Trevor Clifford Caldwell , Zhao Li , Jialin Zhao , Jose Barreiro Silva
CPC classification number: H03M3/422 , H03M1/361 , H03M3/322 , H03M3/344 , H03M3/378 , H03M3/388 , H03M3/414 , H03M3/436 , H03M3/464
Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.
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Patent Agency Ranking
公开(公告)号：US09768793B2
公开(公告)日：2017-09-19
申请号：US15365867
申请日：2016-11-30
Applicant: ANALOG DEVICES GLOBAL
Inventor： Qingdong Meng , Hajime Shibata , Richard E. Schreier , Martin Steven McCormick , Yunzhi Dong , Jose Barreiro Silva , Jialin Zhao , Donald W. Paterson , Wenhua W. Yang
Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.
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公开(公告)号：US10171102B1
公开(公告)日：2019-01-01
申请号：US15865742
申请日：2018-01-09
Applicant: Analog Devices Global Unlimited Company
Inventor： Hajime Shibata , Yunzhi Dong , Zhao Li , Trevor Clifford Caldwell , Wenhua William Yang
Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.
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公开(公告)号：US09843337B1
公开(公告)日：2017-12-12
申请号：US15460433
申请日：2017-03-16
Applicant: Analog Devices Global
Inventor： Zhao Li , Trevor Clifford Caldwell , David Nelson Alldred , Yunzhi Dong , Prawal Man Shrestha , Jialin Zhao , Hajime Shibata , Victor Kozlov , Richard E. Schreier , Wenhua W. Yang
CPC classification number: H03M1/1023 , H03M1/0673 , H03M1/1009 , H03M1/12 , H03M1/361 , H03M3/384 , H03M3/414
Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.
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公开(公告)号：US09762221B2
公开(公告)日：2017-09-12
申请号：US15182430
申请日：2016-06-14
Applicant: ANALOG DEVICES GLOBAL
Inventor： Yunzhi Dong , Victor Kozlov , Wenhua W. Yang , Trevor Clifford Caldwell , Hajime Shibata
CPC classification number: H03K5/14 , H03H7/30 , H03K2005/00254 , H03K2005/00267 , H03M1/001 , H03M1/164 , H03M3/464
Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.
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公开(公告)号：US20160373101A1
公开(公告)日：2016-12-22
申请号：US15182430
申请日：2016-06-14
Applicant: ANALOG DEVICES GLOBAL
Inventor： Yunzhi Dong , VICTOR KOZLOV , WENHUA W. YANG , TREVOR CLIFFORD CALDWELL , HAJIME SHIBATA
CPC classification number: H03K5/14 , H03H7/30 , H03K2005/00254 , H03K2005/00267 , H03M1/001 , H03M1/164 , H03M3/464
Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.
Abstract translation: 在连续时间（CT）模数转换器（ADC）中使用的集成恒定时间延迟电路可以用RC晶格结构来实现，以提供例如无源全通晶格滤波器。 在一些实施例中，可以使用由去耦电容产生的附加极点来提供低通滤波效应。 电阻器 - 电容器“RC”晶格结构可以是恒定电阻电感器“LC”晶格实现的替代。 ADC架构由于RC实现而受益，因为其易于阻抗缩放和面积更小。
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