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    SSD (SOLID STATE DRIVE) DEVICE
    112.
    发明申请
    SSD (SOLID STATE DRIVE) DEVICE 审中-公开
    SSD（固态驱动）设备

    公开(公告)号：US20150081953A1

    公开(公告)日：2015-03-19

    申请号：US14399004

    申请日：2013-03-27

    Applicant: BUFFALO MEMORY CO., LTD.

    Inventor： Yosuke Takata ,  Takayuki Okinaga ,  Noriaki Sugahara

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/1028 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/222 ,  Y02D10/13

    Abstract: The present invention provides an SSD device that uses non-volatile memory as a cache to contribute to reduced power consumption.An SSD (Solid State Drive) device using a flash memory includes n (n≧2) non-volatile memory units 130 and a controller section 11. Each of the non-volatile memory units 130 includes a non-volatile memory different in type from a flash memory. The controller section 11 receives data to be written to the flash memory and stores the received data in the non-volatile memory units 130.

    Abstract translation: 本发明提供了一种使用非易失性存储器作为高速缓存以有助于降低功耗的SSD设备。 使用闪速存储器的SSD（固态硬盘）装置包括n（n≥2）个非易失性存储器单元130和控制器部分11.每个非易失性存储器单元130包括不同类型的非易失性存储器 闪存 控制器部分11接收要写入闪速存储器的数据，并将接收到的数据存储在非易失性存储器单元130中。

    Methods, data storage devices and systems for fragmented firmware table rebuild in a solid state drive
    113.
    发明授权
    Methods, data storage devices and systems for fragmented firmware table rebuild in a solid state drive 有权
    方法，数据存储设备和用于在固态驱动器中重建碎片固件表的系统

    公开(公告)号：US08954694B2

    公开(公告)日：2015-02-10

    申请号：US13677704

    申请日：2012-11-15

    Applicant: Western Digital Technologies, Inc. ,  Skyera, Inc.

    Inventor： Andrew J. Tomlin ,  Justin Jones ,  Rodney N. Mullendore

    IPC: G06F12/00

    CPC classification number: G06F12/0246 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7207

    Abstract: A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals.

    Abstract translation: 数据存储装置包括被配置为存储多个物理页面的多个非易失性存储器装置; 耦合到所述多个存储器件的控制器，其被配置为将数据编程到所述多个存储器件并从其读取数据。 易失性存储器可以耦合到控制器，并且可以被配置为存储包括多个固件表条目的固件表。 控制器可以被配置为将多个固件期刊保持在非易失性存储器设备中。 每个固件日志可以与固件表条目相关联，并且可以包括固件表条目信息。 控制器可以被配置为在启动时读取多个固件日志并且使用每个读取的多个固件期刊中的固件表条目信息来重建固件表。

    FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA WRITING METHOD THEREOF
    114.
    发明申请
    FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA WRITING METHOD THEREOF 审中-公开
    闪存存储系统和控制器及其数据写入方法

    公开(公告)号：US20150039820A1

    公开(公告)日：2015-02-05

    申请号：US14520352

    申请日：2014-10-22

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Lai-Hock Chua ,  Kheng-Chong Tan

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/102

    Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.

    Abstract translation: 提供具有闪速存储器控制器和闪速存储器芯片的闪速存储器存储系统。 闪速存储器控制器将闪存芯片的第二物理单元配置为对应于第一物理单元的中途缓存物理单元，并将对应于第一主机写入命令的第一数据和对应于第二主机写命令的第二数据临时存储在 中间缓存物理单元，其中所述第一和第二数据对应于所述第一物理单元的慢物理地址。 然后，闪速存储器控制器将第一和第二数据从中途高速缓存物理单元同步复制到第一物理单元中，从而缩短将数据写入闪存芯片的时间。

    MAP RECYCLING ACCELERATION
    115.
    发明申请
    MAP RECYCLING ACCELERATION 有权
    地图回收加速

    公开(公告)号：US20140379959A1

    公开(公告)日：2014-12-25

    申请号：US13941820

    申请日：2013-07-15

    Applicant: LSI Corporation

    Inventor： Timothy Canepa ,  Leonid Baryudin ,  Stephen D. Hanna ,  Alex G. Tang

    IPC: G06F12/02

    CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/312 ,  G06F2212/7205

    Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

    Abstract translation: 公开了一种具有处理器和电路的装置。 处理器通常被配置为发起操作以循环非易失性存储器中的多个源块。 电路通常被配置为（i）搜索在映射中的多个级别中的第一级，所述映射定义在与计算机的接口处使用的多个逻辑地址和在存储器中使用的多个物理地址之间的多个翻译 以及（ii）响应于在第一级中检测到包含有效数据的一个或多个要被回收的源块的检测通知处理器。

    STORAGE SYSTEMS AND ALIASED MEMORY
    116.
    发明申请
    STORAGE SYSTEMS AND ALIASED MEMORY 有权
    存储系统和已读存储器

    公开(公告)号：US20140359203A1

    公开(公告)日：2014-12-04

    申请号：US14036298

    申请日：2013-09-25

    Applicant: Microsoft Corporation

    Inventor： William R. Tipton ,  Surendra Verma ,  Landy Wang ,  Malcolm James Smith

    IPC: G06F12/02 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F12/0866 ,  G06F2212/214

    Abstract: Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.

    Abstract translation: 本文描述的主题的方面涉及存储系统和混叠存储器。 在方面，文件系统驱动程序或其他组件可以向存储器控制器发送请求以在两个存储块之间创建别名。 存储器块之一可以用于主存储器，而另一个存储器块可以用于存储系统。 作为响应，存储器控制器可以在存储器块之间创建别名。 在别名被切断之前，当存储器控制器从主存储器中的块接收到对数据的请求时，存储器控制器可以用来自用于存储系统的存储器块的数据进行响应。 存储器控制器还可以实现如本文所述的其他动作。

    System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache
    119.
    发明申请
    System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache 审中-公开
    系统，方法和计算机可读介质，为闪存缓存提供选择性保护和耐久性改进

    公开(公告)号：US20140208005A1

    公开(公告)日：2014-07-24

    申请号：US14071702

    申请日：2013-11-05

    Applicant: LSI Corporation

    Inventor： Horia Simionescu ,  Anant Baderdinni ,  Luca Bert

    IPC: G06F12/02

    CPC classification number: G06F11/1076 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2211/1009 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/214 ,  Y02D10/13

    Abstract: A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information.

    Abstract translation: 高速缓存控制器包括分布在多个固态存储单元上的高速缓存存储器，其中以定义的方式顺序应用高速缓存行填充操作，并且写入操作在条带到达容量时由RAID-5（条带化加奇偶校验）方案保护。 高速缓存存储器响应来自管理主数据存储的存储控制器的数据。 高速缓存存储器根据高速缓存接口接收到的数据的来源或类型不同地排列数据。 行填充操作被放置在高速缓冲存储器中，而不产生和存储对应的奇偶校验信息。 当在高速缓存存储器中存在足够数量的写入操作填充条带构成全部条带时，生成相应的奇偶校验条并存储在指定用于存储奇偶校验信息的条带位置中。

    SOC SYSTEM AND METHOD FOR OPERATING THE SAME
    120.
    发明申请
    SOC SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开
    SOC系统及其操作方法

    公开(公告)号：US20140164688A1

    公开(公告)日：2014-06-12

    申请号：US14089961

    申请日：2013-11-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KI-TAE LEE ,  SANG-HWA JIN ,  SANG-JONG KIM

    IPC: G11C7/10

    CPC classification number: G06F12/08 ,  G06F12/1027 ,  G06F2212/171 ,  G06F2212/214

    Abstract: A SOC system includes a central processing unit; a memory management unit receiving a virtual address from the central processing unit and converting the virtual address into a physical address; a main memory implemented by a volatile memory and directly accessed through the physical address converted by the memory management unit; and a storage implemented by a nonvolatile memory separate from the main memory and including a first area directly accessed through the physical address converted by the memory management unit.

    Abstract translation: SOC系统包括中央处理单元; 存储器管理单元，从所述中央处理单元接收虚拟地址，并将所述虚拟地址转换成物理地址; 由易失性存储器实现并通过由存储器管理单元转换的物理地址直接访问的主存储器; 以及由与主存储器分离的非易失性存储器实现的存储器，并且包括通过由存储器管理单元转换的物理地址直接访问的第一区域。

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