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    Ad hoc digital multi-die polling for peak ICC management
    3.
    发明授权
    Ad hoc digital multi-die polling for peak ICC management 有权
    用于峰值ICC管理的Ad hoc数字多芯片轮询

    公开(公告)号：US09536617B2

    公开(公告)日：2017-01-03

    申请号：US14928992

    申请日：2015-10-30

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Ali Al-Shamma ,  Farookh Moogat ,  Chang Siau ,  Grishma Shah ,  Kenneth Louie ,  Khanh Nguyen ,  Kapil Verma

    IPC: G11C16/06 ,  G11C16/30 ,  G11C16/24

    CPC classification number: G11C16/30 ,  G11C5/02 ,  G11C5/14 ,  G11C5/141 ,  G11C16/24 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2029/1204

    Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

    Abstract translation: 描述了用于减少包括多个存储器管芯的非易失性存储器系统中的峰值电源电流的系统和方法。 在一些情况下，在执行特定存储器操作（例如，编程操作）的多个存储器管芯的第一存储器管芯之前，第一存储器管芯可以轮询多个存储器管芯的其他存储器管芯以确定总的峰值功率 为多个存储管芯提供电流。 响应于检测到多个存储管芯的总峰值电源电流处于或高于峰值电流阈值（例如，大于200mA），第一存储器管芯可能延迟特定存储器操作的性能或减慢 特定内存操作的性能。

    Defect or program disturb detection with full data recovery capability
    5.
    发明授权
    Defect or program disturb detection with full data recovery capability 有权
    缺陷或编程干扰检测具有全面的数据恢复能力

    公开(公告)号：US09053810B2

    公开(公告)日：2015-06-09

    申请号：US13790469

    申请日：2013-03-08

    Applicant: SanDisk Technologies Inc.

    Inventor： Deepanshu Dutta ,  Dana Lee ,  Yan Li ,  Grishma Shah ,  Farookh Moogat ,  Masaaki Higashitani

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3431 ,  G11C2211/5621 ,  G11C2211/5642

    Abstract: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.

    Abstract translation: 用于一组非易失性存储元件的编程操作在程序验证测试通过并且发出程序状态=通过之后确定存储元件是否已经被正确编程。 使用可选的一个或多个重建读取操作的逻辑运算，从与存储元件相关联的锁存器组重建写入数据。 还执行正常读取操作以获得读取数据。 确定读取数据和重建的写入数据之间的一些不匹配，并且基于不匹配的数量确定是否需要重写写入数据。

    Immunity Against Temporary and Short Power Drops in Non-Volatile Memory
    6.
    发明申请
    Immunity Against Temporary and Short Power Drops in Non-Volatile Memory 有权
    对非易失性存储器中的临时和短时间功率放电的抗扰度

    公开(公告)号：US20130265841A1

    公开(公告)日：2013-10-10

    申请号：US13803835

    申请日：2013-03-14

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Yacov Duzly ,  Alon Marcu ,  Farookh Moogat ,  Yan Li ,  Aaron Keith Olbrich

    IPC: G11C5/14

    CPC classification number: G11C7/222 ,  G11C5/14 ,  G11C5/143 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32

    Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

    Abstract translation: 提出了一种机制，存储电路（例如NAND型闪速存储器）可以自主地保护自身免受暂时和短暂的功率下降。 检测机构将电源电压降低到功能电压一段时间以下。 当发生这种事件时，暂停机制被激活，并且在完成最后的微操作（例如编程脉冲）之后，存储器冻结。 当电力再次在运行水平稳定时，恢复暂停运行。 然后可以通过轮询特殊状态位在出现这种电压降时通知存储器控制器。 可以如何实现暂停的示例包括更改时钟信号和暂停较大操作的子阶段。

    AD HOC DIGITAL MULTI-DIE POLLING FOR PEAK ICC MANAGEMENT
    7.
    发明申请
    AD HOC DIGITAL MULTI-DIE POLLING FOR PEAK ICC MANAGEMENT 有权
    用于峰值ICC管理的AD HOC DIGITAL MULTI DIE POLLING

    公开(公告)号：US20160293264A1

    公开(公告)日：2016-10-06

    申请号：US14928992

    申请日：2015-10-30

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Ali Al-Shamma ,  Farookh Moogat ,  Chang Siau ,  Grishma Shah ,  Kenneth Louie ,  Khanh Nguyen ,  Kapil Verma

    IPC: G11C16/30 ,  G11C16/24

    CPC classification number: G11C16/30 ,  G11C5/02 ,  G11C5/14 ,  G11C5/141 ,  G11C16/24 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2029/1204

    Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

    Abstract translation: 描述了用于减少包括多个存储器管芯的非易失性存储器系统中的峰值电源电流的系统和方法。 在一些情况下，在执行特定存储器操作（例如，编程操作）的多个存储器管芯的第一存储器管芯之前，第一存储器管芯可以轮询多个存储器管芯的其他存储器管芯以确定总的峰值功率 为多个存储管芯提供电流。 响应于检测到多个存储管芯的总峰值电源电流处于或高于峰值电流阈值（例如，大于200mA），第一存储器管芯可能延迟特定存储器操作的性能或减慢 特定内存操作的性能。

    NON-VOLATILE MEMORY AND METHOD WITH PEAK CURRENT CONTROL
    9.
    发明申请
    NON-VOLATILE MEMORY AND METHOD WITH PEAK CURRENT CONTROL 有权
    具有峰值电流控制的非易失性存储器和方法

    公开(公告)号：US20150023116A1

    公开(公告)日：2015-01-22

    申请号：US14507647

    申请日：2014-10-06

    Applicant: SanDisk Technologies Inc.

    Inventor： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

    IPC: G11C5/14

    CPC classification number: G11C5/14 ,  G11C16/30

    Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

    Abstract translation: 具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。 负载信号总线以与系统功率容量成比例的强度被拉高。 每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。 因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。 因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。 当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

    Verify Operations Using Different Sense Node Voltages In A Memory Device
    10.
    发明申请
    Verify Operations Using Different Sense Node Voltages In A Memory Device 有权
    使用不同的感应节点电压验证操作在存储器件中

    公开(公告)号：US20170076812A1

    公开(公告)日：2017-03-16

    申请号：US14849879

    申请日：2015-09-10

    Applicant: SanDisk Technologies Inc.

    Inventor： Alexander Chu ,  Jong Hak Yuh ,  Kwang-Ho Kim ,  Yenlung Li ,  Farookh Moogat

    IPC: G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

    CPC classification number: G11C16/3459 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/5621

    Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.

    Abstract translation: 存储器件中的检测电路可以在感测过程中被预充电到不同的电平，以减少用于感测的时间量。 例如，在程序操作中，存储单元处于快速编程模式，直到其阈值电压超过数据状态的偏移验证电压（VO）为止。 偏移验证电压低于数据状态的最终验证电压（VF）。 当阈值电压在VO和VF之间时，存储单元处于慢速编程模式。 对于一个存储器单元，在VO的验证测试可以通过对于另一个存储器单元的VF进行验证测试来同时执行，其中，对于另一个存储单元，通过将用于所述一个存储器单元的感测电路预充电到比另一存储单元的感测电路更高的电压。 可以使用普通的放电时间和跳闸条件。

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