公开(公告)号：US20180182737A1

公开(公告)日：2018-06-28

申请号：US15850975

申请日：2017-12-21

Applicant: Buffalo Memory Co, Ltd.

Inventor： YU NAKASE ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Kazuki Makuni ,  Takeshi Kotegawa ,  Noriaki Sugahara

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.

公开(公告)号：US09632714B2

公开(公告)日：2017-04-25

申请号：US14699838

申请日：2015-04-29

Applicant: BUFFALO MEMORY CO., LTD.

Inventor： Kazuki Makuni ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Yosuke Takata ,  Noriaki Sugahara

IPC: G06F3/06 ,  G06F12/02 ,  G06F1/30 ,  G06F12/0873

CPC classification number: G06F3/0619 ,  G06F1/30 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0873 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/3042 ,  G06F2212/313 ,  G06F2212/604 ,  G06F2212/72

Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.

公开(公告)号：US09866219B2

公开(公告)日：2018-01-09

申请号：US14908339

申请日：2014-06-09

Applicant: Meisei Gakuen ,  BUFFALO MEMORY CO., LTD.

Inventor： Kanji Otsuka ,  Yoichi Sato ,  Takayuki Okinaga ,  Shuichiro Azuma

IPC: H03K19/17 ,  H03K19/21 ,  G06F1/02

CPC classification number: H03K19/21 ,  G06F1/02

Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.

公开(公告)号：US09223695B2

公开(公告)日：2015-12-29

申请号：US13927881

申请日：2013-06-26

Applicant: Buffalo Memory Co., Ltd.

Inventor： Kazuki Makuni ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Yosuke Takata ,  Noriaki Sugahara

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7208

Abstract: An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

Abstract translation: 一种包括NAND型闪速存储器的信息处理装置; 被配置为控制向/从NAND型闪速存储器写入/读取数据的电路; 以及被配置为将信息处理设备连接到主机设备的接口。 电路被配置为基于是否经由接口从主机设备接收到重写命令来确定是否擦除存储在NAND型闪存中的特定区域中的数据; 并且当确定通过在包括特定区域的物理块中去除NAND型闪速存储器中的电荷来确定擦除数据时，擦除包括特定区域的物理块。

公开(公告)号：US20140068157A1

公开(公告)日：2014-03-06

申请号：US13963501

申请日：2013-08-09

Applicant: BUFFALO MEMORY CO., LTD.

Inventor： Kazuki Makuni ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Yosuke Takata ,  Noriaki Sugahara

IPC: G06F12/02

CPC classification number: G06F3/0619 ,  G06F1/30 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0873 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/3042 ,  G06F2212/313 ,  G06F2212/604 ,  G06F2212/72

Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.

Abstract translation: 使用闪速存储器并且包括类型与闪存不同的非易失性存储器的固态驱动器（SSD）装置。 SSD设备接收要写入闪速存储器的数据; 将所接收的数据存储在非易失性存储器中; 将存储在非易失性存储器中的数据存储到闪速存储器; 并且在所述非易失性存储器中存储指示要在所述非易失性存储器中存储所接收的数据的同时进行的任务的流程的数据流，并将存储在所述非易失性存储器中的数据存储到所述闪速存储器。

公开(公告)号：US09189388B2

公开(公告)日：2015-11-17

申请号：US13927881

申请日：2013-06-26

Applicant: Buffalo Memory Co., Ltd.

Inventor： Kazuki Makuni ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Yosuke Takata ,  Noriaki Sugahara

IPC: G06F12/02

Abstract: An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

公开(公告)号：US09063845B2

公开(公告)日：2015-06-23

申请号：US13963501

申请日：2013-08-09

Applicant: BUFFALO MEMORY CO., LTD.

Inventor： Kazuki Makuni ,  Takayuki Okinaga ,  Shuichiro Azuma ,  Yosuke Takata ,  Noriaki Sugahara

IPC: G06F12/02 ,  G06F1/30

CPC classification number: G06F3/0619 ,  G06F1/30 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0873 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/3042 ,  G06F2212/313 ,  G06F2212/604 ,  G06F2212/72

Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.

Abstract translation: 使用闪速存储器并且包括类型与闪存不同的非易失性存储器的固态驱动器（SSD）装置。 SSD设备接收要写入闪速存储器的数据; 将所接收的数据存储在非易失性存储器中; 将存储在非易失性存储器中的数据存储到闪速存储器; 并且在所述非易失性存储器中存储指示要在所述非易失性存储器中存储所接收的数据的同时进行的任务的流程的数据流，并将存储在所述非易失性存储器中的数据存储到所述闪速存储器。

公开(公告)号：US20150081953A1

公开(公告)日：2015-03-19

申请号：US14399004

申请日：2013-03-27

Applicant: BUFFALO MEMORY CO., LTD.

Inventor： Yosuke Takata ,  Takayuki Okinaga ,  Noriaki Sugahara

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1028 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/222 ,  Y02D10/13

Abstract: The present invention provides an SSD device that uses non-volatile memory as a cache to contribute to reduced power consumption.An SSD (Solid State Drive) device using a flash memory includes n (n≧2) non-volatile memory units 130 and a controller section 11. Each of the non-volatile memory units 130 includes a non-volatile memory different in type from a flash memory. The controller section 11 receives data to be written to the flash memory and stores the received data in the non-volatile memory units 130.

Abstract translation: 本发明提供了一种使用非易失性存储器作为高速缓存以有助于降低功耗的SSD设备。 使用闪速存储器的SSD（固态硬盘）装置包括n（n≥2）个非易失性存储器单元130和控制器部分11.每个非易失性存储器单元130包括不同类型的非易失性存储器 闪存 控制器部分11接收要写入闪速存储器的数据，并将接收到的数据存储在非易失性存储器单元130中。