公开(公告)号：US09866219B2

公开(公告)日：2018-01-09

申请号：US14908339

申请日：2014-06-09

Applicant: Meisei Gakuen ,  BUFFALO MEMORY CO., LTD.

Inventor： Kanji Otsuka ,  Yoichi Sato ,  Takayuki Okinaga ,  Shuichiro Azuma

IPC: H03K19/17 ,  H03K19/21 ,  G06F1/02

CPC classification number: H03K19/21 ,  G06F1/02

Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.