公开(公告)号：US20180204837A1

公开(公告)日：2018-07-19

申请号：US15923097

申请日：2018-03-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Balasubramanian Pranatharthiharan ,  Alexander Reznicek ,  Charan V. Surisetty

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28035 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

公开(公告)号：US20180197793A1

公开(公告)日：2018-07-12

申请号：US15802929

申请日：2017-11-03

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Zuoguang Liu ,  Gen Tsutsui ,  Heng Wu

IPC: H01L21/8238 ,  H01L29/165 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823437 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

公开(公告)号：US20180197792A1

公开(公告)日：2018-07-12

申请号：US15404466

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Zuoguang Liu ,  Gen Tsutsui ,  Heng Wu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823437 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

公开(公告)号：US10020257B2

公开(公告)日：2018-07-10

申请号：US15797561

申请日：2017-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Juntao Li

IPC: H01L29/66 ,  H01L23/525 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/06 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01C17/006 ,  H01H69/022 ,  H01L21/31051 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

公开(公告)号：US10020051B1

公开(公告)日：2018-07-10

申请号：US15635811

申请日：2017-06-28

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: H01L21/00 ,  G11C11/54 ,  H01L27/105 ,  H01L23/528 ,  H01L27/092 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66 ,  G11C11/40

CPC classification number: G11C11/54 ,  G11C11/40 ,  G11C11/405 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1211 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/66545

Abstract: A memory device including a plurality of memory cells arranged in a crossbar configuration for a neural network is provided. Each of the memory cells includes a readout transistor, a charging transistor, a discharging transistor, and a stack capacitor array connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.

公开(公告)号：US20180188858A1

公开(公告)日：2018-07-05

申请号：US15736230

申请日：2017-04-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  Beijing BOE Optoelectronics Technology Co., Ltd.

Inventor： Yong Zhang ,  Yue Li ,  Shijun Wang ,  Zhenhua Lv ,  Wenjun Xiao

IPC: G06F3/047 ,  G06F3/041 ,  G09G5/04 ,  G09G3/20 ,  H01L21/8234

CPC classification number: G06F3/047 ,  G06F3/0412 ,  G06F2203/0339 ,  G06F2203/04103 ,  G09G3/2003 ,  G09G5/04 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2320/0666 ,  H01L21/823437 ,  H01L21/823475

Abstract: Disclosed is a display panel, a method of manufacturing the same, and a display device. The display panel includes: a plurality of sub pixels arranged in rows and columns, wherein sub pixels in one of two adjacent rows of sub pixels are offset from sub pixels in the other row, respectively, in a column direction, and each sub pixel has a different color from an adjacent sub pixel; a plurality of data lines extending in the column direction in a column gap between the sub pixels; a plurality of touch signal lines provided in a gap between the sub pixels; and a plurality of touch detection electrodes electrically connected to the plurality of touch signal lines, respectively. The touch detection electrodes are used as a common electrode of the sub pixels, and the touch signal line is provided in a film layer between the common electrode and a pixel electrode of the sub pixel, respectively. A part of the film layer in a thickness direction of the display panel is provided between the touch control signal line and the pixel electrode of the sub pixel.

公开(公告)号：US10014295B2

公开(公告)日：2018-07-03

申请号：US15344256

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. Surisetty ,  Soon-Cheon Seo ,  Tenko Yamashita

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.

公开(公告)号：US10008415B2

公开(公告)日：2018-06-26

申请号：US15419346

申请日：2017-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/84 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US20180175193A1

公开(公告)日：2018-06-21

申请号：US15835703

申请日：2017-12-08

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Praveen Raghavan ,  Odysseas Zografos

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/66666 ,  H01L29/7831

Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.

公开(公告)号：US09997412B1

公开(公告)日：2018-06-12

申请号：US15646300

申请日：2017-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ho Bae ,  Jaeseok Kim ,  Hoyoung Kim ,  Boun Yoon ,  KyungTae Lee ,  Kwansung Kim ,  Eunji Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.