公开(公告)号：US20170310076A1

公开(公告)日：2017-10-26

申请号：US15490528

申请日：2017-04-18

申请人： The Board of Trustees of the University of Illinois

发明人： Can Bayram ,  Richard Liu

IPC分类号： H01S5/02 ,  H01S5/323 ,  H01L31/0304 ,  H01L29/20 ,  H01L33/32

CPC分类号： H01S5/0207 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02609 ,  H01L29/2003 ,  H01L31/03044 ,  H01L33/16 ,  H01L33/32 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/3013 ,  H01S5/3031 ,  H01S5/32341 ,  H01S2301/173 ,  H01S2304/00 ,  H01S2304/04

摘要： A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.

公开(公告)号：US09799793B2

公开(公告)日：2017-10-24

申请号：US15391948

申请日：2016-12-28

申请人： Sensor Electronic Technology, Inc.

发明人： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L29/06 ,  H01L33/00 ,  H01L33/32 ,  H01L33/12 ,  H01L29/778 ,  H01L29/66 ,  H01L33/20 ,  H01L33/24

CPC分类号： H01L33/0025 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

摘要： A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US20170301823A1

公开(公告)日：2017-10-19

申请号：US15634583

申请日：2017-06-27

申请人： GLO AB

发明人： Carl Patrik Theodor Svensson ,  Nathan Gardner

IPC分类号： H01L33/00 ,  H01L33/06 ,  H01L33/24 ,  H01L33/44

CPC分类号： H01L33/0075 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/06 ,  H01L33/08 ,  H01L33/16 ,  H01L33/24 ,  H01L33/44 ,  H01L2933/0025

摘要： A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires.

公开(公告)号：US20170301772A1

公开(公告)日：2017-10-19

申请号：US15489083

申请日：2017-04-17

申请人： Robert M. Radway ,  Tomas A. Palacios

发明人： Robert M. Radway ,  Tomas A. Palacios

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/205 ,  H01L29/10 ,  H01L21/308 ,  H01L21/306 ,  H01L21/18 ,  H01L21/683 ,  H01L29/20

CPC分类号： H01L29/66462 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/6835 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381

摘要： A wafer bonding technique to fabricate GaN devices is disclosed. In this technique, a GaN layer (or a GaN stack including at least one GaN layer) is fabricated on a first substrate (e.g., a silicon substrate) and has a high quality surface with a dislocation density less than 1010/cm2. The assembly of the first substrate and the GaN layer is then bonded to a second substrate (e.g., a carbide substrate or an AlN substrate) by coupling the high quality surface to the second substrate. The high quality of the GaN surface in contact with the carbide substrate creates a good thermal contact. The first substrate is etched away to expose a GaN surface for further processing, such as electrode formation.

公开(公告)号：US09786498B2

公开(公告)日：2017-10-10

申请号：US15119703

申请日：2015-02-12

申请人： OSRAM Opto Semiconductors GmbH

发明人： Juergen Off ,  Matthias Peter ,  Thomas Lehnhardt ,  Werner Bergbauer

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  C30B25/18 ,  C30B29/40

CPC分类号： H01L21/0254 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02645 ,  H01L21/02658

摘要： Described is a method for producing a nitride compound semiconductor layer, involving the steps of:—depositing a first seed layer (1) comprising a nitride compound semiconductor material on a substrate (10);—desorbing at least some of the nitride compound semiconductor material in the first seed layer from the substrate (10);—depositing a second seed layer (2) comprising a nitride compound semiconductor material; and—growing the nitride compound semiconductor layer (3) containing a nitride compound semiconductor material onto the second seed layer (2).

公开(公告)号：US20170287709A1

公开(公告)日：2017-10-05

申请号：US15090904

申请日：2016-04-05

申请人： Infineon Technologies Austria AG

发明人： Simone Lavanga ,  Uttiya Chowdhury

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L29/66 ,  H01L29/778 ,  H01L29/15 ,  H01L29/205

CPC分类号： H01L21/02507 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02636 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/205 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/7784 ,  H01L29/7786

摘要： A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.

公开(公告)号：US20170263741A1

公开(公告)日：2017-09-14

申请号：US15231387

申请日：2016-08-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yasuhiro ISOBE ,  Hung HUNG ,  Akira YOSHIOKA

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02579 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes a first stacked portion above a substrate, the first stacked portion comprising a first nitride semiconductor layer containing aluminum and a second nitride semiconductor layer containing carbon, a third nitride semiconductor layer on the first stacked portion, the third nitride semiconductor layer containing carbon and having a greater thickness than each of the first and second nitride semiconductor layers, the third nitride semiconductor layer having a lower carbon concentration than the second nitride semiconductor layer, a second stacked portion on the third nitride semiconductor, the second stacked portion comprising a fourth nitride semiconductor layer containing aluminum and a fifth nitride semiconductor layer containing carbon, a sixth nitride semiconductor layer on the second stacked portion, a seventh nitride semiconductor layer on the sixth nitride semiconductor layer and containing aluminum, and a first electrode on the seventh nitride layer.

公开(公告)号：US20170256405A1

公开(公告)日：2017-09-07

申请号：US15599376

申请日：2017-05-18

申请人： STC.UNM

发明人： Seung-Chang Lee ,  Steven R.J. Brueck

IPC分类号： H01L21/02 ,  H01L29/267

CPC分类号： H01L21/02513 ,  C30B7/005 ,  C30B23/025 ,  C30B25/04 ,  C30B25/18 ,  C30B25/183 ,  C30B29/40 ,  C30B29/42 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02636 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/0665 ,  H01L29/0688 ,  H01L29/267

摘要： Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially- single- particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

公开(公告)号：US09755062B2

公开(公告)日：2017-09-05

申请号：US15389255

申请日：2016-12-22

申请人： Intel Corporation

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/268 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/36

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US20170229611A1

公开(公告)日：2017-08-10

申请号：US15496887

申请日：2017-04-25

申请人： Sensor Electronic Technology, Inc.

发明人： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L33/12 ,  H01L21/02 ,  H01L21/308

CPC分类号： H01L21/308 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/158 ,  H01L29/2003 ,  H01L29/66075 ,  H01L33/007 ,  H01L33/12

摘要： A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.