- 专利标题: III-N material structure for gate-recessed transistors
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申请号: US15389255申请日: 2016-12-22
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公开(公告)号: US09755062B2公开(公告)日: 2017-09-05
- 发明人: Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt P.C.
- 主分类号: H01L21/268
- IPC分类号: H01L21/268 ; H01L29/778 ; H01L29/20 ; H01L29/205 ; H01L29/40 ; H01L21/02 ; H01L21/306 ; H01L21/311 ; H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L29/36
摘要:
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
公开/授权文献
- US20170104094A1 III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS 公开/授权日:2017-04-13
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