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    Logic compatible RRAM structure and process
    91.
    发明授权
    Logic compatible RRAM structure and process 有权
    逻辑兼容的RRAM结构和过程

    公开(公告)号：US09231197B2

    公开(公告)日：2016-01-05

    申请号：US13831629

    申请日：2013-03-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口保形地形成的第一电极，保形地形成在第一电极上的电阻层，保形地形成在电阻层上的间隔层，保形地形成在电阻层上的第二电极 以及保形地形成在第二电极上的第二电介质层，第二介电层包括第二开口。 第一介电层形成在包括第一金属层的基板上。 第一电极和电阻层共同地包括第一距离超过第一开口延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过第一开口的第二唇缘区域。 间隔层从第二距离延伸到第一距离。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。

    Memory circuit and method of programming memory circuit
    92.
    发明授权
    Memory circuit and method of programming memory circuit 有权
    存储器电路和编程存储器电路的方法

    公开(公告)号：US09224470B1

    公开(公告)日：2015-12-29

    申请号：US14452177

    申请日：2014-08-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yi-Chieh Chiu ,  Chih-Yang Chang ,  Tassa Yang ,  Wen-Ting Chu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2213/82

    Abstract: A method includes applying a first voltage setting to a first node and a second node of a selected memory cell for a first predetermined period of time in response to a command for programming a first logical state to the selected memory cell. A first stored logical state of the selected memory cell is obtained after the applying the first voltage setting operation. If the first stored logical state differs from the first logical state, a second voltage setting is applied to the first node and the second node of the selected memory cell; and a first retrial is performed. The first retrial includes applying the first voltage setting to the first node and the second node of the selected memory cell for the first predetermined period of time.

    Abstract translation: 一种方法包括响应于将第一逻辑状态编程到所选择的存储器单元的命令，将第一电压设置应用于所选择的存储器单元的第一节点和第二节点第一预定时间段。 在施加第一电压设置操作之后，获得所选存储单元的第一存储逻辑状态。 如果第一存储的逻辑状态与第一逻辑状态不同，则第二电压设置被施加到所选择的存储器单元的第一节点和第二节点; 并执行第一次重试。 第一重试包括在第一预定时间段内将第一电压设置应用于所选存储器单元的第一节点和第二节点。

    One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers
    93.
    发明授权
    One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers 有权
    一个具有双间隔器的晶体管和一个电阻（1T1R）随机存取存储器（RAM）结构

    公开(公告)号：US09099647B2

    公开(公告)日：2015-08-04

    申请号：US14607955

    申请日：2015-01-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Wen Liao ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Hsia-Wei Chen ,  Ching-Pei Hsieh

    IPC: H01L21/20 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1608 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

    Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

    Abstract translation: 本公开提供了制造电阻随机存取存储器（RRAM）单元的方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部部分的底部电极，底部电极上的电阻材料层具有与底部电极的顶部部分的宽度相同的宽度; 覆盖在所述底部电极上的覆盖层，围绕所述覆盖层的第一间隔物和顶部电极，围绕所述底部电极和所述第一间隔物的顶部以及所述顶部电极的第二间隔物。 RRAM单元还包括将RRAM结构的顶部电极连接到金属层的导电材料。

    Resistive memory reset
    94.
    发明授权
    Resistive memory reset 有权
    电阻式存储器复位

    公开(公告)号：US08908415B2

    公开(公告)日：2014-12-09

    申请号：US13782632

    申请日：2013-03-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chin-Chieh Yang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Hsia-Wei Chen

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/79

    Abstract: A resistive memory cell includes a switch and a resistive switching device. The switch includes a first terminal connected to a select line and a gate terminal connected to a word line. The resistive switching device is connected between a second terminal of the switch and a bit line. The resistive switching device is resettable by having a positive bias applied to the word line and a negative bias applied to the bit line.

    Abstract translation: 电阻式存储单元包括开关和电阻开关器件。 开关包括连接到选择线的第一端子和连接到字线的栅极端子。 电阻式开关器件连接在开关的第二端和位线之间。 电阻开关器件可通过对字线施加正偏压而将负偏压施加到位线来复位。

    LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS
    96.
    发明申请
    LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS 有权
    逻辑兼容的RRAM结构和过程

    公开(公告)号：US20140131654A1

    公开(公告)日：2014-05-15

    申请号：US13831629

    申请日：2013-03-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口保形地形成的第一电极，保形地形成在第一电极上的电阻层，保形地形成在电阻层上的间隔层，保形地形成在电阻层上的第二电极 以及保形地形成在第二电极上的第二电介质层，第二介电层包括第二开口。 第一介电层形成在包括第一金属层的基板上。 第一电极和电阻层共同地包括第一距离超过第一开口延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过第一开口的第二唇缘区域。 间隔层从第二距离延伸到第一距离。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。

    Metal landing on top electrode of RRAM
    97.
    发明授权
    Metal landing on top electrode of RRAM 有权

    公开(公告)号：US12256652B2

    公开(公告)日：2025-03-18

    申请号：US18443368

    申请日：2024-02-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Wen-Ting Chu

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

    RRAM bottom electrode
    98.
    发明授权
    RRAM bottom electrode 有权

    公开(公告)号：US12041861B2

    公开(公告)日：2024-07-16

    申请号：US17533411

    申请日：2021-11-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: H10N70/841 ,  H10N70/063 ,  H10B63/30 ,  H10N70/231 ,  H10N70/826

    Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

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